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n ano100(a) mar 31 , 201 5 page 1 of 95 revision v 1 . 00 NANO100 (a) series datasheet arm ? cortex ? - m 32 - bit microcontroller numicro ? family n ano 100 (a) series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omi ssions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
n ano100(a) mar 31 , 201 5 page 2 of 95 revision v 1 . 00 NANO100 (a) series datasheet table of c ontents 1 g eneral description ................................ ................................ ................................ ..... 7 2 f eatures ................................ ................................ ................................ ............................. 9 2.1 NANO100 features C base line ................................ ................................ ................... 9 2.2 nano120 features C usb connectivity line ................................ .............................. 14 3 parts information list and p in c onfiguration ................................ ................ 19 3.1 numicro ? NANO100 series selection code ................................ ............................... 19 3.2 numicro ? NANO100 products selection guide ................................ .......................... 20 3.2.1 numicro ? NANO100 base line selection guide ................................ ............................. 20 3.2.2 numicro ? nano120 usb connectivity line selection guide ................................ ......... 20 3.3 pin configuration ................................ ................................ ................................ ........ 21 3.3.1 numicro ? NANO100 pin diagram ................................ ................................ ................... 21 3.3.2 numicro ? nano120 pin diagram ................................ ................................ ................... 25 3.4 pin description ................................ ................................ ................................ ........... 29 3.4.1 numicro ? NANO100 pin description ................................ ................................ ............... 29 3.4.2 numicro ? nano120 pin description ................................ ................................ ............... 40 4 block diagram ................................ ................................ ................................ ................ 51 4.1 NANO100 block diagram ................................ ................................ ............................ 51 4. 2 nano120 block diagram ................................ ................................ ............................ 52 5 functional descripti on ................................ ................................ .............................. 53 5.1 arm ? cortex? - m0 core ................................ ................................ ........................... 53 5.1.1 overview ................................ ................................ ................................ ........................ 53 5.1.2 features ................................ ................................ ................................ ......................... 53 5.2 memory organization ................................ ................................ ................................ . 55 5.2.1 overview ................................ ................................ ................................ ........................ 55 5.2.2 memory m ap ................................ ................................ ................................ .................. 55 5.3 nested vectored interrupt controller (nvic) ................................ ............................. 57 5.3.1 overview ................................ ................................ ................................ ........................ 57 5.3.2 features ................................ ................................ ................................ ......................... 57 5.4 system manager ................................ ................................ ................................ ........ 58 5.4.1 overview ................................ ................................ ................................ ........................ 58 5.4.2 features ................................ ................................ ................................ ......................... 58 5.5 clock controller ................................ ................................ ................................ .......... 59 5.5.1 overview ................................ ................................ ................................ ........................ 59 5.5.2 features ................................ ................................ ................................ ......................... 59 5.6 flash memory controller (fmc) ................................ ................................ .............. 60 5.6.1 overview ................................ ................................ ................................ ........................ 60 5.6.2 features ................................ ................................ ................................ ......................... 60 5.7 external bus interface ................................ ................................ ................................ 61 5.7.1 overview ................................ ................................ ................................ ........................ 61 5.7.2 features ................................ ................................ ................................ ......................... 61 5.8 general purpose i/o controller ................................ ................................ .................. 61
n ano100(a) mar 31 , 201 5 page 3 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.8.1 overview ................................ ................................ ................................ ........................ 61 5.8.2 features ................................ ................................ ................................ ......................... 61 5.9 dma contro ller ................................ ................................ ................................ ........... 62 5.9.1 overview ................................ ................................ ................................ ........................ 62 5.9.2 features ................................ ................................ ................................ ......................... 62 5.10 timer con troller ................................ ................................ ................................ .......... 63 5.10.1 overview ................................ ................................ ................................ ...................... 63 5.10.2 features ................................ ................................ ................................ ....................... 63 5.11 pulse width modulation (pwm) ................................ ................................ ................. 63 5.11.1 overview ................................ ................................ ................................ ...................... 63 5.11.2 features ................................ ................................ ................................ ....................... 64 5.12 watchdog timer controller ................................ ................................ ........................ 66 5.12.1 overview ................................ ................................ ................................ ...................... 66 5.12.2 featu res ................................ ................................ ................................ ....................... 66 5.13 rtc ................................ ................................ ................................ ............................ 67 5.13.1 overview ................................ ................................ ................................ ...................... 67 5.13.2 featu res ................................ ................................ ................................ ....................... 67 5.14 uart controller ................................ ................................ ................................ ......... 68 5.14.1 overview ................................ ................................ ................................ ...................... 68 5.14.2 features ................................ ................................ ................................ ....................... 68 5.15 smart card host interface (sc) ................................ ................................ ................. 69 5.15.1 overview ................................ ................................ ................................ ...................... 69 5.15.2 features ................................ ................................ ................................ ....................... 69 5.16 i 2 c ................................ ................................ ................................ ............................... 69 5.16.1 overview ................................ ................................ ................................ ...................... 69 5.16.2 features ................................ ................................ ................................ ....................... 71 5.17 spi ................................ ................................ ................................ .............................. 72 5.17.1 overview ................................ ................................ ................................ ...................... 72 5.17.2 features ................................ ................................ ................................ ....................... 7 2 5.18 i 2 s ................................ ................................ ................................ ............................... 73 5.18.1 overview ................................ ................................ ................................ ...................... 73 5.18.2 features ................................ ................................ ................................ ....................... 73 5.19 usb ................................ ................................ ................................ ............................ 74 5.19.1 overview ................................ ................................ ................................ ...................... 74 5.19.2 features ................................ ................................ ................................ ....................... 74 5.20 analog to digital converter (adc) ................................ ................................ ............. 75 5.20.1 overview ................................ ................................ ................................ ...................... 75 5.20.2 featu res ................................ ................................ ................................ ....................... 75 6 application circuit ................................ ................................ ................................ ....... 76 7 electrical character istic ................................ ................................ ....................... 77 7.1 absolute maximum ratings ................................ ................................ ........................ 77 7.2 dc electrical characteristics ................................ ................................ ...................... 78 7.3 ac electrical characteristics ................................ ................................ ...................... 82
n ano100(a) mar 31 , 201 5 page 4 of 95 revision v 1 . 00 NANO100 (a) series datasheet 7.3.1 external input clock ................................ ................................ ................................ ....... 82 7.3.2 external 4~24 mhz xtal oscillator ................................ ................................ ............... 82 7.3.3 external 32.768 khz crystal ................................ ................................ ........................... 83 7.3.4 internal 12 mhz oscillator ................................ ................................ .............................. 83 7.3.5 internal 10 khz oscillator ................................ ................................ ............................... 83 7.4 analog characteristics ................................ ................................ ............................... 83 7. 4.1 12 - bit adc ................................ ................................ ................................ ...................... 83 7.4.2 brown - out detector ................................ ................................ ................................ ......... 84 7.4.3 power - on reset ................................ ................................ ................................ ............. 85 7.4.4 temperature sensor ................................ ................................ ................................ ....... 85 7.4. 5 internal voltage reference ................................ ................................ ............................. 85 7.4.6 usb phy specifications ................................ ................................ ................................ . 85 8 package dimensions ................................ ................................ ................................ ..... 87 8.1 lqfp100 (14x14x1.4 mm footprint 2.0 mm) ................................ .............................. 87 8.2 lqfp64 (7x7x1.4 mm footprint 2.0 mm) ................................ ................................ .... 88 8.3 lqfp48 (7x7x1.4 mm footprint 2.0 mm) ................................ ................................ .... 90 8.4 qfn33 (5x5x0.8 mm footprint 0.5 mm) ................................ ................................ ...... 91 9 revision history ................................ ................................ ................................ ............ 93
n ano100(a) mar 31 , 201 5 page 5 of 95 revision v 1 . 00 NANO100 (a) series datasheet list of figures figure 3 - 1 numicro tm NANO100 series selection code ................................ ................................ . 19 figure 3 - 2 numicro tm NANO100 lqfp 100 - pin assignment ................................ .......................... 21 figure 3 - 3 numicro tm NANO100 lqfp 64 - pin assignment ................................ ............................ 22 figure 3 - 4 numicro tm NANO100 lqfp 48 - pin assignment ................................ ............................ 23 figure 3 - 5 numicro tm NANO100 qfn 33 - pin assignment ................................ .............................. 24 figure 3 - 6 numicro tm nano120 lqfp 100 - pin as signment ................................ .......................... 25 figure 3 - 7 numicro tm nano120 lqfp 64 - pin assignment ................................ ............................ 26 figure 3 - 8 numicro tm nano120 lqfp 48 - pin assignment ................................ ............................ 27 figure 3 - 9 numicro tm nano120 qfn 33 - pin assignment ................................ .............................. 28 figure 4 - 1 numicro tm NANO100 block diagram ................................ ................................ ............. 51 figure 4 - 2 numicro tm nano120 block diagram ................................ ................................ ............. 52 figure 6 - 1 m0 functional block ................................ ................................ ................................ ..... 53 figure 8 - 1 typical crystal application circuit ................................ ................................ ................ 83
n ano100(a) mar 31 , 201 5 page 6 of 95 revision v 1 . 00 NANO100 (a) series datasheet list of tables table 1 - 1 connectivity support table ................................ ................................ .............................. 8 table 3 - 1 NANO100 base line selection table ................................ ................................ ............. 20 table 3 - 2 nano120 usb connectivity line selection table ................................ ......................... 20
n ano100(a) mar 31 , 201 5 page 7 of 95 revision v 1 . 00 NANO100 (a) series datasheet 1 g eneral description the nano 100 series ultra - low power 32 - bit microcontroller is embedded with arm ? cortex? - m0 core operate d at a wide voltage range from 1.8v to 3.6v and runs up to 32 mhz frequency with 32k/64k - byte embedded f lash and 8k/16k - byte embedded sram. i ntegrat ing usb 2.0 full - speed function, rtc, 1 2 - bit sar adc, and provide s high performance connectivity peripheral interfaces such as uart, spi, i2c, i2s, gpios, ebi (external bus interface) for external memory - mapped d evice access and iso - 7816 - 3 for smart card , the nano 100 series s upport s brown - out d etector, p ower - d own mode with ram retention and fast wake - up via many peripheral interfaces. the nano 100 series provide s low power voltage, low power consumption, low stand by current, high integration peripherals , high - efficiency operation , fast wake - up function and lowest cost 32 - bit microco ntrollers. the nano 100 series is suitable for a wide range of battery device applications such as: ? portable data collector ? portable me dical monitor ? portable rfid reader ? portable barcode scanner ? security alarm system ? system supervisors ? power metering ? usb accessories ? smart card reader ? wireless game control device ? iptv remote smart keyboard ? wireless sensors node device (wsn) ? wireless rf4ce remote control ? wireless audio ? wireless automatic meter reader (amr) ? electronic toll collection(etc) th e nano 100 base line , an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core , operates at wide voltage range from 1.8v to 3.6v and runs up to 32 mhz frequency with 32k/64k byte s embedded flash and 8k/16k byte s embedded sram. it integrate s rtc, 8 - channels 1 2 - bit sar adc, and provide s high performance connectivity peripheral interfaces such as 2x uart, 3x spi, 2x i2c, i2s , gpios, ebi (external bus interface) for external memory - mapped device access and 2x iso - 7816 - 3 for smart card. th e nano 100 base line s upport s brown - out d etector, power - down mode with ram retention and fast wake - up via many peripheral interfaces. t he nano 120 usb c onnectivity line , an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core , operates at wide voltage range from 1.8v to 3.6v and runs up to 32 mhz frequency with 32k/64k byte s embedded flash and 8k/16k byte s embedded sram. it integrate s usb 2.0 full - speed device function, rtc, 8 - channels 1 2 - bit sar adc, and provide s high performance connectivity peripheral interfaces such as 2x uart, 3x spi, 2x i2c, i2s, gpios, ebi (external bus interface) for external memory - mapped device acce ss and 2x iso - 7816 - 3 for smart card. t he nano 120 usb c onnectivity line s upport s brown - out d etector, power - down mode with ram retention and fast wake - up via many peripheral interfaces.
n ano100(a) mar 31 , 201 5 page 8 of 95 revision v 1 . 00 NANO100 (a) series datasheet product line uart spi i2c i2s usb adc rtc ebi sc timer NANO100 nano120 table 1 - 1 connectivity support table
n ano100(a) mar 31 , 201 5 page 9 of 95 revision v 1 . 00 NANO100 (a) series datasheet 2 f eatures the equipped features are dependent on the product line and their sub products. 2.1 NANO100 features C base line ? core ? arm ? cortex? - m0 core running up to 32 mhz ? one 24 - bit system timer ? supports l ow p ower s leep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? buil t - in 2.5v/2.0v/1.7v bod for wide operating voltage range operation ? flash eprom memory ? run s up to 32 mhz with zero wait state for discontinuous address read acces s ? 64k/32k byte s application program memory (aprom ) ? 4 k b in system programming (isp) loader program memory (ldrom ) ? programmable data flash start address and memory size with 512 bytes page erase un it ? in system program (isp)/in application program (iap) to up date on - chip flash epro m ? sram memory ? 16k/8k byte s embedded sram ? support s dma mode ? dma : support s 5 channels : one vdma channel and 4 pdma channels ? vdma ? memory - to - memory transfer ? support s block transfer with stride ? support s word/half - word/byte boundary address ? support s address direction: increment and decrement ? p dma ? peripheral - to - mem ory, memory - to - peripheral, and memory - to - memory transfer ? support s word boundary address ? support s word alignment transfer length in memory - to - memory mode ? support s word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? support s word/half - word/byte transfer data width from/to peripheral ? support s address direction: increment, fixed, and wrap around
n ano100(a) mar 31 , 201 5 page 10 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? clock control ? flexible se lection for different applications ? buil t - in 12 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wake - up idle operation ? low power 10 khz osc for watchdog and low power system operation ? support s one pll, up to 96 mhz, f or high performance system operation (32 mhz) and usb application (48 mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc function and low power system operation ? gpio ? three i/o modes: ? push - pull outpu t ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin configured as interrupt source with edge/level setting ? s upport s hi gh d river and h igh s ink i / o mode ? support s input 5v tolerance (except adc shared pins pc.6 and pc.7 ) ? timer ? support s 4 sets of 32 - bit timers , each with 24 - bit up - counting timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot , output toggle and periodic operation modes ? i nternal trigger event to adc module ? s upport s pdma mode ? timer can wake system up from power down or idle mode ? watchdog timer ? clock source from lirc (internal 10 khz low speed oscillator clock) ? s electable time out period from 1.6 ms ~ 26 sec ( depend ing on clock source ) ? interrupt or reset selectable when watchdog time - out ? w ake system up from p ower - down or i dle mode ? rtc ? support s software compensation by setting frequency compensate register (fcr) ? support s rtc counter (second, minute, hour) and calendar counter (day, month, year) ? support s alarm registe rs (second, minute, hour, day, month, year) ? selectable 12 - hour or 24 - hour mode
n ano100(a) mar 31 , 201 5 page 11 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? automatic leap year recognition ? support s periodic time tick interrupt with 8 period ic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? w ake system up from p ower - down or idle mode ? s upport s 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/capture ? support s 2 pwm modules, each has two 16 - bit pwm generators ? p rovide s eight pwm outputs or four complementary paired pwm outputs ? ea ch pwm generator equipped with one clock divider, one 8 - bit prescaler , two clock selector s , and one dead - z one generator for complementary paired pwm ? up to eight 16 - bit digital capture timers (shared with pwm timers) , and provide s eight capture inputs (risi ng, falling, or both) ? support s o ne - shot and c ontinuous mode ? support s capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? uart ports with flow control (tx, rx, cts n and rts n ) ? support s irda (sir) function ? support s lin function ? support s rs - 485 9 bit mode and direction control. ? programmable baud rate generator ? support s pdma mode ? w ake system up from p ower - down or idle mode ? spi ? up to three sets of spi controller ? master up to 16 mhz, and slave up to 6 mhz ? support s spi/microwire master/slave mode ? full duplex synchronous serial data transfer ? variable length of transfer data from 4 to 32 bits ? msb or lsb first data transfer ? r x and t x on both rising or falling edge of serial clock independently ? two slave/device select lines when spi controller is used as the master, and 1 slave/device select line when spi controller is used as the slave ? support s byte suspend mode in 32 - bit transmission ? s upport s two channel pdma requests, one for transmit and another for receive ? support s three wire mode, no slave select signal, bi - direction interface ? w ake system up from p ower - down or idle mode
n ano100(a) mar 31 , 201 5 page 12 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? i2 c ? up to two sets of i2c device ? master/slave up to 1 mbit/s ? bi - directional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter request ing the i2c interrupt if the i2c bus hangs up and timer - out counter overflow s ? programmable clocks allow ing for versatile rate control ? supports 7 - bit addressin g mod e ? support s multiple address recognition (four slave address es with mask option) ? i2s ? interface with external audio codec ? operate d as either m aster or slave mode ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i2s and msb justified data format ? provides t wo 8 word fifo data buffers : one for transmit ting and the other for receiv ing ? generates interrupt requests when buffer levels cross a programmable boundary ? support s two pdma requests : one for transmit tin g and the other for receiv ing ? adc ? 1 2 - bit sar a dc ? up to 8 - ch single - end ed input from external pin ? one internal channel from avdd, avss, temp sensor, and inte rnal reference voltage ? s upport s s ingle s can , s ingle c ycle s can , and c ontinuous s can mode ? each channel with individual result register ? only s can on enabled channels ? threshold voltage detection (comparator function ) ? conversion start ed by software programming or external input ? support s pdma mode ? s upport s up to four timer time - out events (trm0_ch0, tmr 0_ch1, tmr1_ch0
n ano100(a) mar 31 , 201 5 page 13 of 95 revision v 1 . 00 NANO100 (a) series datasheet and tmr1_ch1) to enable adc ? smartcard (sc) ? compliant to iso - 7816 - 3 t=0, t=1 ? support s up to two iso - 7816 - 3 ports ? separate s receive/ transmit 4 byte s entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 26 7 etu) ? a 24 - bit and two 8 bit time out counter s for answer to request (atr) and waiting times processing ? support s auto inverse convention functio n ? support s transmitter and receiver error re try and error limit function ? support s hardware activation sequence process ? support s hardware warm reset sequence process ? support s hardware deactivation sequence process ? support s hardware auto deactivation sequence when detect the card is removal ? ebi (external bus interface) support ? accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode ? support s 8bit/16bit data width ? support s byte write in 16 - bit d ata w idth mode ? one built - in temperature sensor with 1 resolutio n ? 96 - bit unique id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 100 - pin (14x14) / 64 - pin (7x7) / 48 - pin (7x7) / qfn 33 - pin(5x5)
n ano100(a) mar 31 , 201 5 page 14 of 95 revision v 1 . 00 NANO100 (a) series datasheet 2.2 nano120 features C usb connectivity line ? core ? arm ? cortex? - m0 core running up to 32 mhz ? one 24 - bit system timer ? supports l ow p ower s leep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? buil t - in 2.5v/2.0v/1.7v bod for wide operating voltage range operation ? flash eprom memory ? run s up to 32 mhz with zero wait state for discontinuous address read acces s. ? 64k/32 k bytes application program memory (aprom ) ? 4 k b in system programming (isp) loader program memory (ldrom ) ? programmable data flash start address and memory size with 512 bytes page erase un it ? in system program (isp)/in application program (iap) to update on chip flash epro m ? sram memory ? 16k/8 k bytes embedded sram ? support pdma mode ? dma : support 5 channels : one vdma channel and 4 pdma channels ? vdma ? memory - to - memory transfer ? support block transfer with stride ? support word/half - word/byte boundary address ? support address direction: increment and decrement ? p dma ? peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? support word boundar y address ? support word alignment transfer length in memory - to - memory mode ? support word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? support word/half - word/byte transfer data width from/to peripheral ? support address: increment, fixed, and wrap around ? clock control ? flexible selection for different applications
n ano100(a) mar 31 , 201 5 page 15 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? buil t - in 12 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wake - up operation ? low power 10 khz osc for watchdog a nd low power system operation ? support one pll, up to 96 mhz, for high performance system operation (32mhz) and usb application (48mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc function and low power system operation ? gpio ? three i/o modes: ? push - pull output ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin can be configured as interrupt source with edge/level setting ? high driver and high sink io mode support ? support input 5v tolerance (except adc shared pins pc.6 and pc.7 ) ? timer ? support 4 sets of 32 - bit timers , each with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot , output toggle and periodic operat ion modes ? i nternal trigger event to adc module ? support pdma mode ? w ake system up from p ower - down or i dle mode ? watchdog timer ? clock source from lirc. (internal 10 khz low speed oscillator clock) ? s electable time out period from 1.6 ms ~ 26 sec (depend ing on clock source ) ? interrupt or reset selectable on watchdog time - out ? w ake system up from p ower - down or idle mode ? rtc ? support s software compensation by setting frequency compensate register (fcr) ? support s rtc counter (second, minute, hour) and calendar coun ter (day, month, year) ? support s alarm registers (second, minute, hour, day, month, year) ? selectable 12 - hour or 24 - hour mode ? automatic leap year recognition ? support s periodic time tick interrupt with 8 period ic options 1/128, 1/64, 1/32,
n ano100(a) mar 31 , 201 5 page 16 of 95 revision v 1 . 00 NANO100 (a) series datasheet 1/16, 1/8, 1/4, 1/2 and 1 second ? w ake system up from p ower - down or idle mode ? s upport 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/capture ? support 2 pwm module, each has two 16 - bit pwm generators ? p rovide eight pwm outputs or four complementary paired pwm outputs ? each pwm generator equipped with one clock divider, one 8 - bit prescaler , two clock selector s , and one dead - zone generator for complementary paired pwm ? up to eight 16 - bit digital capture timers (shared with pwm timers) prov ide eight rising/falling capture inputs ? support one shot and continuous mode ? support capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? uart ports with flow control (tx, rx, cts n and rts n ) ? support s irda (sir) function ? support s lin function ? support s rs - 485 9 bit mode and direction control. (low density only) ? programmable baud rate generator ? support s pdma mode ? w ake system up from p ower - down or idle mode ? spi ? up to three sets of spi controller ? master up to 16 mhz, and slave up to 6 mhz ? support s spi/microwire master/slave mode ? full duplex synchronous serial data transfer ? variable length of transfer data from 4 to 32 bits ? msb or lsb first data transfer ? r x and t x on both rising or falling edge of serial clock independently ? two slave/device select l ines when spi controller is as the master, and 1 slave/device select line when spi controller is as the slave ? support s byte suspend mode in 32 - bit transmission ? s upport s two channel pdma requests, one for transmit and another for receive ? support s three wire , no slave select signal, bi - direction interface ? w ake system up from p ower - down or idle mode ? i2 c ? up to two sets of i2c device
n ano100(a) mar 31 , 201 5 page 17 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? master/slave up to 1mbit/s ? bi - directional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitratio n between simultaneously transmitting masters without corruption of serial data on the bus ? ser ial clock synchronization allow ing devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter request ing the i2c interrupt if the i2c bus hangs up and timer - out counter overflow s ? programmable clocks allow versatile rate control ? supports 7 - bit addressing mod e ? support s multiple address recognition (four slave address es with mask option) ? i2s ? interface with external audio codec ? operate d as either master or slave mode ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i2s and m sb justified data format ? provides t wo 8 word fifo data buffers : one for transmit ting and the other for receiv ing ? generates interrupt requests when buffer levels cross a programmable boundary ? support s two pdma requests : one for transmit ting and the other fo r receiv ing ? adc ? 1 2 - bit sar adc with 8 00k sps ? up to 8 - ch single - end input from external pin. ? one internal channel from avdd, avss, temp sensor, and internal reference voltage. ? support s s ingle scan , single cycle scan , and continuous scan modes ? each channel with individual result register ? only s can on enabled channels ? threshold voltage detection (comparator function ) ? conversion start by software programming or external input ? support s pdma mode ? s upport s up to four timer time - out events (tmr0, tmr1, tmr 2 , tmr 3 ) to enable adc ? smartcard (sc)
n ano100(a) mar 31 , 201 5 page 18 of 95 revision v 1 . 00 NANO100 (a) series datasheet ? compliant to iso - 7816 - 3 t=0, t=1 ? supports up to two iso - 7816 - 3 ports ? separate s receive / transmit 4 byte s entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 26 7 etu) ? a 24 - bit and two 8 bit time out counter for answer to request (atr) and waiting times processing ? supports auto inverse convention functio n ? supports transmitter and receiver error retry and error limit fu nction ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detect the card is removal ? usb 2.0 full - speed device ? one set of usb 2.0 fs device 12mbps ? on - chip usb transceiver ? provide s 1 interrupt source with 4 interrupt events ? supports control, bulk in/out, interrupt and isochronous transfers ? auto suspend function when no bus signaling for 3 ms ? provide 6 programmable endpo ints ? include 512 bytes internal sram as usb buffer ? provide remote wake - up capability ? one built - in temperature sensor with 1 resolutio n ? 96 - bit unique id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 100 - pin (14x14) / 64 - pin (7x7) / 48 - pin (7x7) / qfn 33 - pin(5x5)
n ano100(a) mar 31 , 201 5 page 19 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3 parts information list and p in c onfiguration 3.1 numicro ? figure 3 - 1 numicro tm nano1 00 series s election c ode
n ano100(a) mar 31 , 201 5 page 20 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3.2 numicro ? 3.2.1 numicro ? qfn33: 5x5mm ; lqfp48: 7x7mm ; lqfp64*: 7x7mm table 3 - 1 NANO100 base line s election table 3.2.2 numicro ? qfn33: 5x5mm ; lqfp48: 7x7mm ; lqfp64*: 7x7mm table 3 - 2 nano120 usb connectivity line selection table uart spi i 2 c usb NANO100zc2an 32k 8k configurable 4k up to 26 4 2 2 2 - - 2 5 v - v 4 - v qfn33 NANO100zd2an 64k 8k configurable 4k up to 26 4 2 2 2 - - 2 5 v - v 4 - v qfn33 NANO100zd3an 64k 16k configurable 4k up to 26 4 2 2 2 - - 2 5 v - v 4 - v qfn33 NANO100lc2an 32k 8k configurable 4k up to 37 4 2 3 2 - 1 4 8 v - v 4 2 v lqfp48 NANO100ld2an 64k 8k configurable 4k up to 37 4 2 3 2 - 1 4 8 v - v 4 2 v lqfp48 NANO100ld3an 64k 16k configurable 4k up to 37 4 2 3 2 - 1 4 8 v - v 4 2 v lqfp48 NANO100sd2an 64k 8k configurable 4k up to 51 4 2 3 2 - 1 8 8 v v v 4 2 v lqfp64* NANO100sd3an 64k 16k configurable 4k up to 51 4 2 3 2 - 1 8 8 v v v 4 2 v lqfp64* 12-bit adc i/o timer (32-bit) irc 10khz 12mhz package part no. flash (kbytes) sram (kbytes) iso- 7816-3 icp isp iap isp rom (kbytes) i 2 s connectivity pwm data flash ebi pdma rtc uart spi i 2 c usb nano120zc2an 32k 8k configurable 4k up to 22 4 2 2 2 1 - 2 5 - - v 4 2 v qfn33 nano120zd2an 64k 8k configurable 4k up to 22 4 2 2 2 1 - 2 5 - - v 4 2 v qfn33 nano120zd3an 64k 16k configurable 4k up to 22 4 2 2 2 1 - 2 5 - - v 4 2 v qfn33 nano120lc2an 32k 8k configurable 4k up to 33 4 2 3 2 1 1 4 8 v - v 4 2 v lqfp48 nano120ld2an 64k 8k configurable 4k up to 33 4 2 3 2 1 1 4 8 v - v 4 2 v lqfp48 nano120ld3an 64k 16k configurable 4k up to 33 4 2 3 2 1 1 4 8 v - v 4 2 v lqfp48 nano120sd2an 64k 8k configurable 4k up to 47 4 2 3 2 1 1 8 8 v v v 4 2 v lqfp64* nano120sd3an 64k 16k configurable 4k up to 47 4 2 3 2 1 1 8 8 v v v 4 2 v lqfp64* package icp isp iap iso- 7816-3 rtc irc 10khz 12mhz timer (32-bit) connectivity i 2 s pwm sram (kbytes) 12-bit adc isp rom (kbytes) i/o flash (kbytes) ebi data flash pdma part no.
n ano100(a) mar 31 , 201 5 page 21 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3.3 pin c onfiguration 3.3.1 numicro ? numicro ? n ano100 lqfp 100 - pin 3.3.1.1 figure 3 - 2 numicro tm NANO100 lqfp 100 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 p d . 1 5 p d . 1 4 p d . 7 p d . 6 p b . 3 p b . 2 p b . 1 p b . 0 p e . 7 p e . 8 p e . 9 p e . 1 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 p c . 1 1 n a n o 1 0 0 l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p d . 1 2 p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 1 1 p e . 1 2 p c . 4 p c . 5 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p f . 4 p f . 5 p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 v r e f
n ano100(a) mar 31 , 201 5 page 22 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano100 lqfp 64 - pin 3.3.1.2 figure 3 - 3 numicro tm NANO100 lqfp 64 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 p c . 1 1 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p d . 1 5 p d . 1 4 p d . 7 p d . 6 p b . 3 p b . 2 p b . 1 p b . 0 n a n o 1 0 0 l q f p 6 4 - p i n
n ano100(a) mar 31 , 201 5 page 23 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano100 lqfp 48 - pin 3.3.1.3 figure 3 - 4 numicro tm na no100 lqfp 48 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 l d o v d d v s s p c . 7 p c . 6 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 a v d d p v s s p b . 9 p b . 1 0 p b . 1 1 p e . 5 p b . 3 p b . 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n a n o 1 0 0 l q f p 4 8 - p i n p b . 1 p b . 0 p c . 0 p c . 1 p c . 2 p c . 3
n ano100(a) mar 31 , 201 5 page 24 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano100 qfn 33 - pin 3.3.1.4 figure 3 - 5 numicro tm NANO100 qfn 33 - pin assignment p a . 5 a v d d x 3 2 i p a . 1 1 p a . 1 0 l d o v d d v s s p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t x 3 2 o p a . 4 p a . 3 i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 4 p a . 1 5 p c . 6 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 3 v s s 3 2 3 1 3 0 2 9 2 8 8 7 6 5 4 3 2 1 1 9 2 0 2 1 2 2 2 3 2 4 p c . 0 p c . 1 p c . 2 p c . 3 p a . 9 p a . 8 p b . 1 p b . 0 p b . 3 p b . 2 p a . 2 p a . 0 n a n o 1 0 0 q f n 3 3 - p i n 9 1 7 1 8 2 7 2 6 2 5
n ano100(a) mar 31 , 201 5 page 25 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3.3.2 numicro ? numicro ? n ano120 lqfp 100 - pin 3.3.2.1 figure 3 - 6 numicro tm nan o120 lqfp 100 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 p d . 1 5 p d . 1 4 p d . 7 p d . 6 p b . 3 p b . 2 p b . 1 p b . 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 p c . 1 1 n a n o 1 2 0 l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p d . 1 2 p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p c . 4 p c . 5 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p f . 4 p f . 5 p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 v r e f u s b _ d p u s b _ d m v d d 3 3 v b u s p e . 7 p e . 8
n ano100(a) mar 31 , 201 5 page 26 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano1 2 0 lqfp 64 - pin 3.3.2.2 figure 3 - 7 numicro tm nano120 lqfp 64 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 p c . 1 1 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p b . 3 p b . 2 p b . 1 p b . 0 d + d - v d d 3 3 v b u s n a n o 1 2 0 l q f p 6 4 - p i n
n ano100(a) mar 31 , 201 5 page 27 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano120 lqfp 48 - pin 3.3.2.3 figure 3 - 8 numicro tm nano120 lqfp 48 - pin assignment p a . 5 p a . 6 p a . 7 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 l d o v d d v s s p c . 7 p c . 6 p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 a v d d p v s s 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n a n o 1 2 0 l q f p 4 8 - p i n p c . 0 p c . 1 p c . 2 p c . 3 p b . 3 p b . 2 p b . 1 p b . 0 d + d - v d d 3 3 v b u s
n ano100(a) mar 31 , 201 5 page 28 of 95 revision v 1 . 00 NANO100 (a) series datasheet numicro ? n ano120 qf n 33 - pin 3.3.2.4 figure 3 - 9 numicro tm nano120 qfn 33 - pin assignment p a . 5 a v d d p a . 1 1 p a . 1 0 p a . 9 l d o v d d v s s p b . 1 5 x t 1 _ o u t x t 1 _ i n / r e s e t p v s s p a . 4 p a . 3 i c e _ c k / p f . 1 i c e _ d a t / p f . 0 p a . 1 4 p a . 1 5 p c . 6 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 3 v s s 3 2 3 1 3 0 2 9 2 8 8 7 6 5 4 3 2 1 1 9 2 0 2 1 2 2 2 3 2 4 p c . 0 p c . 1 p c . 2 p c . 3 p a . 8 p b . 4 v d d 3 3 v b u s d + d - p a . 2 p a . 0 n a n o 1 2 0 q f n 3 3 - p i n 9 1 7 1 8 2 7 2 6 2 5
n ano100(a) mar 31 , 201 5 page 29 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3.4 pin d escription 3.4.1 numicro ? pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 1 pe.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 2 pe.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 3 pe.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 4 1 pb.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. spiss21 o spi2 2nd slave select pin n int0 i external interrupt 0 input pin 5 2 pb.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. ad1 i/o ebi address/data bus bit 1 6 3 1 pb.12 i/o digital gpio pin ad0 i/ o ebi address/data bus bit0 clko o frequency divider output pin 7 4 2 32 x32o o external 32.768 khz crystal output pin 8 5 3 1 x32i i external 32.768 khz crystal input pin 9 6 4 2 pa.11 i/o digital gpio pin i2c1sck i/o i2c 1 clock pin nrd o ebi read enable output pin sc0rst o smartcard0 rst pin mosi20 i/o spi 2 1st mosi (master out, slave in) pin 10 7 5 3 pa.10 i/o digital gpio pin i2c1sda i/o i2c 1 data i/o pin nwr o ebi write enable output pin sc0pwr o smartcard0 power pin miso20 i/o spi2 1st miso (master in, slave out) pi n 11 8 6 4 pa.9 i/o digital gpio pin
n ano100(a) mar 31 , 201 5 page 30 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin i2c0scl i/o i 2 c0 clock pin sc0dat i/o smartcard0 data pin spiclk 2 o spi 2 serial clock pin 12 9 7 5 pa.8 i/o digital gpio pin i2c0sda i/o i 2 c0 data i/o pin sc0clk o smartcard0 clock pin spiss 2 0 o spi2 1st slave select pin 13 pd.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 14 pd.9 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 15 pd.10 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 16 pd.11 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 17 pd.12 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 18 pd.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 19 10 8 pb.4 i/o digital gpio pin rx1 i uart1 d ata receiver input pin sc0cd i smartcard0 card detect pin spiss20 o spi2 1st slave select pin 20 11 9 pb.5 i/o digital gpio pin tx1 o uart1 d ata transmitter output pin spiclk 2 o spi2 serial clock pin 21 12 pb.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. rts n 1 o uart1 r equest to send output pin ale o ebi address latch enable output pin miso20 i/o spi2 2nd miso (master in, slave out) pin
n ano100(a) mar 31 , 201 5 page 31 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 22 13 pb.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. cts n 1 i uart1 clear to send input pi n ncs o ebi chip select enable output pin mosi20 i/o spi2 1st mosi (master out, slave in) pin 23 14 10 6 ldo p ldo output pin 24 15 11 7 vdd p power supply for i/o ports and ldo source 25 16 12 8 vss p ground 26 pe.12 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 27 pe.11 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 28 pe.10 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 29 pe.9 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 30 pe.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 31 pe.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 32 17 13 9 pb.0 i/o digital gpio pin rx0 i uart0 data receiver input pin mosi10 i/o spi1 1st mosi (master out, slave in) pin 33 18 14 10 pb.1 i/o digital gpio pin tx0 o uart0 data transmitter output pin miso10 i/o spi1 1st miso (master in, slave out) pin 34 19 15 11 pb.2 i/o digital gpio pin rtsn0 o uart0 request to send output pin nwrl o ebi low byte write enable output pin spiclk 1 o spi1 serial clock pin 35 20 16 12 pb.3 i/o digital gpio pin
n ano100(a) mar 31 , 201 5 page 32 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin ctsn0 i uart0 clear to send input pin nwrh o ebi high byte write enable output pin spiss 1 0 o spi1 1st slave select pin 36 21 pd.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 37 22 pd.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 38 23 pd.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 39 24 pd.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 40 pc.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi01 o spi0 2nd mosi (master out, slave in) pin 41 pc.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso01 i spi0 2nd miso (master in, slave out) pin 42 25 17 13 pc.3 i/o digital gpio pin mosi00 o spi0 1st mosi (master out, slave in) pin i2sdo o i2 s data output sc1rst o smartcard1 rst pin 43 26 18 14 pc.2 i/o digital gpio pin miso00 i spi0 1st miso (master in, slave out) pin i2sdi i i2 s data input sc1pwr o smartcard1 pwr pin 44 27 19 15 pc.1 i/o digital gpio pin spiclk0 i/o spi0 serial clock pin i2sbclk i/o i2s bit clock pin sc1dat i/o smartcard1 data pin 45 28 20 16 pc.0 i/o digital gpio pin spiss00 i/o spi0 1st slave select pin
n ano100(a) mar 31 , 201 5 page 33 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin i2slrclk i/o i 2 s left right channel clock sc1clk o smartcard1 clock pin 46 pe.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 47 29 21 pe.5 i/o digital gpio pin pwm 1ch1 i/o pwm 1 channel1 output 48 30 22 pb.11 i/o digital gpio pin pwm 1ch0 i/o pwm 1 channel0 output tm r 3 o timer3 external counter input miso00 i/o spi0 1st miso (master in, slave out) pin 49 31 23 pb.10 i/o digital gpio pin spiss01 i/o spi0 2nd slave select pin tm r 2 o timer2 external counter input mosi00 i/o spi0 1st mosi (master out, slave in) pin 50 32 24 pb.9 i/o digital gpio pin spiss11 i/o spi1 2nd slave select pin tm r 1 o timer1 external counter input nint0 i external interrupt 0 input pin 51 pe.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi00 i/o spi0 1st mosi (master out, slave in) pin 52 pe.3 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso00 i/o spi0 1st miso (master in, slave out) pin 53 pe.2 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. spiclk 0 o spi0 serial clock pin 54 pe.1 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. pwm 1ch3 i/o pwm 1 channel3 output spiss00 o spi0 1st slave select pin
n ano100(a) mar 31 , 201 5 page 34 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 55 pe.0 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. pwm 1ch2 i/o pwm 1 channel2 output i2smclk o i2s master clock output pin 56 pc.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi11 o spi1 2nd mosi (master out, slave in) pin pwm1ch! o pwm1 channel1 output snooper i snooper pin nint0 i external interrupt 0 i2c0sck o i2c0 clock pin 57 pc.12 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso11 i spi1 2nd miso (master in, slave out) pin pwm1ch0 o pwm1 channel0 output nint0 i external interrupt 0 input pin i2c 0 sda i/o i2c 0 data i/o pin 58 33 pc.11 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. mosi10 o spi1 1st mosi (master out, slave in) pin tx1 o uart1 data transmitter output pin 59 34 pc.10 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. miso10 i spi1 1st miso (master in, slave out) pin rx1 i uart1 data receiver input pin 60 35 pc.9 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. spiclk 1 i/o spi1 serial clock pin i2c1sck i/o i2 c1 clock pin 61 36 pc.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package.
n ano100(a) mar 31 , 201 5 page 35 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin spiss10 i/o spi1 1st slave select pin mclk o ebi external clock output pin i2c1sda i/o i2 c1 data i/o pin 62 37 25 17 pa.15 i/o digital gpio pin pwm 0ch3 i/o pwm 0 channel3 output i2smclk o i2s master clock output pin tc3 i timer3 capture input tx 0 o uart0 data transmitter output pin 63 38 26 18 pa.14 i/o digital gpio pin pwm 0ch2 i/o pwm 0 channel2 output ad1 5 i/o ebi address/data bus bit 1 5 tc2 i timer 2 capture input rx 0 i uart0 data receiver input pin 64 39 27 pa.13 i/o digital gpio pin pwm 0ch1 i/o pwm 0 channel1 output ad14 i/o ebi address/data bus bit 14 tc1 i timer1 capture input i2c 0 sc k i/o i2c 0 clock pin 65 40 28 pa.12 i/o digital gpio pin pwm0 ch0 i/o pwm0 channel0 output ad13 i/o ebi address/data bus bit 13 tc0 i timer 0 capture input i2c0sda i/o i2c 0 data i/o pin 66 41 29 19 ice_dat i/o serial wired debugger data pin pf.0 i/o digital gpio pin nint0 i external interrupt 0 input pin 67 42 30 20 ice_ck i serial wired debugger clock pin pf.1 i/o digital gpio pin clko o frequency divider output pin nint1 i external interrupt 1 input pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 33 vss p ground
n ano100(a) mar 31 , 201 5 page 36 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 70 43 31 avss ap ground pin for analog circuit 71 44 32 21 pa.0 i/o digital gpio pin adc0 ai adc analog input 0 72 45 33 pa.1 i/o digital gpio pin adc1 ai adc analog input 1 ad12 i/o ebi address/data bus bit 12 73 46 34 22 pa.2 i/o digital gpio pin adc2 ai adc analog input 2 ad11 i/o ebi address/data bus bit 11 rx1 i uart1 data receiver input pin 74 47 35 23 pa.3 i/o digital gpio pin adc3 ai adc analog input 3 ad10 i/o ebi address/data bus bit 10 tx1 o uart1 data transmitter output pin 75 48 36 24 pa.4 i/o digital gpio pin adc4 ai adc analog input 4 ad9 i/o ebi address/data bus bit 9 i2c 0 sda i/o i2c 0 data i/o pin 76 49 37 25 pa.5 i/o digital gpio pin adc5 ai adc analog input 5 ad8 i/o ebi address/data bus bit 8 i2c0sc k i/o i2c0 clock pin 77 50 38 pa.6 i/o digital gpio pin adc6 ai adc analog input 6 ad7 i/o ebi address/data bus bit 7 tc3 i timer3 capture input pwm0ch3 o pwm0 channel3 output 78 51 39 pa.7 i/o digital gpio pin adc7 ai adc analog input 7 ad6 i/o ebi address/data bus bit 6 tc2 i timer2 capture input pwm0ch2 o pwm0 channel2 output
n ano100(a) mar 31 , 201 5 page 37 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin 79 vref ap voltage reference input for adc 80 52 40 26 avdd ap power supply for internal analog circuit 81 pd.0 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. rx1 i uart1 data receiver input pin spiss2 0 i/o spi2 2nd slave select pin sc1clk o smartcard1 clock pin 82 pd.1 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. tx1 o uart1 data transmitter output pin spiclk 2 i/o spi2 serial clock pin sc1dat i/o smartcard1 data pin. 83 pd.2 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. rtsn1 o uart1 request to send output pin i2slrclk i/o i2s left right channel clock miso20 i spi2 1st miso (master in, slave out) pin sc1pwr o smartcard1 power pin 84 pd.3 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. ctsn1 i uart1 clear to send input pin i2sbclk i/o i2s bit clock pin mosi20 o spi2 1st mosi (master out, slave in) pin sc1rst o smartcard1 rst pin 85 pd.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2sdi i i2s data input miso21 i spi2 2nd miso (master in, slave out) pin sc1cd i smartcard1 card detect 86 pd.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package.
n ano100(a) mar 31 , 201 5 page 38 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin i2sdo o i2s data output mosi21 o spi2 2nd mosi (master out, slave in) pin 87 53 41 pc.7 i/o digital gpio pin ad5 i/o ebi address/data bus bit 5 tc1 i timer1 capture input pwm0ch1 o pwm1 channel1 output 88 54 42 27 pc.6 i/o digital gpio pin ad4 i/o ebi address/data bus bit 4 tc0 i timer 0 capture input sc1cd i smartcard1 card detect pin pwm0ch0 o pwm0 channel0 output 89 55 pc.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. ad3 i/o ebi address/data bus bit 3 tc0 i timer0 capture input pwm1ch2 o pwm1 channel1 output 90 56 pc.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. ad2 i /o ebi address/data bus bit 2 pwm1ch3 i/o pwm1 channel3 output 91 57 43 28 pb.15 i/o digital gpio pin n int1 i external interrupt 1 input pin snooper i snooper pin 92 58 44 29 xt1_out o external 4~24 mhz crystal output pin 93 59 45 30 xt1_in i external 4~24 mhz crystal input pin 94 60 46 31 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 pf.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package.
n ano100(a) mar 31 , 201 5 page 39 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin qfn 33 - pin i2c 0 sda i/o i2c 0 data i/o pin 98 p f.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2c 0 sc k i/o i 2 c 0 clock pin 99 63 47 pvss p pll ground 100 64 48 pb.8 i/o digital gpio pin adctrg i adc external trigger input. tm r 0 i timer0 external counter input nint0 i external interrupt 0 input pin note: pin type : i = digital input ; o = digital output; ai = analog input; ao = analog output; p = power pin; ap = analog power
n ano100(a) mar 31 , 201 5 page 40 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3.4.2 numicro ? pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 1 pe.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 2 pe.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 3 pe.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 4 1 pb.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. n int0 i external interrupt 0 input pin spiss21 o spi2 2nd slave select pin 5 2 pb.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. ad1 i/o ebi address/data bus bit 1 6 3 1 pb.12 i/o digital gpio pin ad0 i/ o ebi address/data bus bit0 clko o frequency divider output pin 7 4 2 x32o o external 32.768 khz crystal output pin 8 5 3 x32i i external 32.768 khz crystal input pin 9 6 4 1 pa.11 i/o digital gpio pin i2c1sck i/o i2c 1 clock pin nrd o ebi read enable output pin sc0rst o smartcard0 rst pin mosi20 i/o spi 2 1st mosi (master out, slave in) pin 10 7 5 2 pa.10 i/o digital gpio pin i2c1sda i/o i2c 1 data i/o pin nwr o ebi write enable output pin sc0pwr o smartcard0 power pin miso20 i/o spi2 1st miso (master in, slave out) pi n 11 8 6 3 pa.9 i/o digital gpio pin i2c0scl i/o i 2 c0 clock pin
n ano100(a) mar 31 , 201 5 page 41 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 sc0dat i/o smartcard0 data pin spiclk 2 o spi 2 serial clock pin 12 9 7 4 pa.8 i/o digital gpio pin i2c0sda i/o i 2 c0 data i/o pin sc0clk o smartcard0 clock pin spiss 2 0 o spi2 1st slave select pin 13 pd.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 14 pd.9 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 15 pd.10 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 16 pd.11 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 17 pd.12 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 18 pd.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 19 10 8 5 pb.4 i/o digital gpio pin rx1 i uart1 d ata receiver input pin sc0cd i smartcard0 card detect pin spiss20 o spi2 1st slave select pin 20 11 9 pb.5 i/o digital gpio pin tx1 o uart1 d ata transmitter output pin spiclk 2 o spi2 serial clock pin 21 12 pb.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. rts n 1 o uart1 r equest to send output pin ale o ebi address latch enable output pin miso20 i/o spi2 2nd miso (master in, slave out) pin
n ano100(a) mar 31 , 201 5 page 42 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 22 13 pb.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. cts n 1 i uart1 clear to send input pi n ncs o ebi chip select enable output pin mosi20 i/o spi2 1st mosi (master out, slave in) pin 23 14 10 6 ldo p ldo output pin 24 15 11 7 vdd p power supply for i/o ports and ldo source 25 16 12 8 vss p ground 26 pe.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 27 pe.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 28 17 13 9 vbus usb power supply: from usb host or hub. 29 18 14 10 vdd33 usb internal power regulator output 3.3v decoupling pin 30 19 15 11 d - usb usb differential signal d - 31 20 16 12 d+ usb usb differential signal d+ 32 21 1 7 pb.0 i/o digital gpio pin rx0 i uart0 data receiver input pin mosi10 i/o spi1 1st mosi (master out, slave in) pin 33 22 1 8 pb.1 i/o digital gpio pin tx0 o uart0 data transmitter output pin miso10 i/o spi1 1st miso (master in, slave out) pin 34 23 1 9 pb.2 i/o digital gpio pin rtsn0 o uart0 request to send output pin nwrl o ebi low byte write enable output pin spiclk 1 o spi1 serial clock pin 35 2 4 20 pb.3 i/o digital gpio pin ctsn0 i uart0 clear to send input pin nwrh o ebi high byte write enable output pin spiss 1 0 o spi1 1st slave select pin
n ano100(a) mar 31 , 201 5 page 43 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 36 pd.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 37 pd.7 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 38 pd.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 39 pd.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. 40 pc.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi01 o spi0 2nd mosi (master out, slave in) pin 41 pc.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso01 i spi0 2nd miso (master in, slave out) pin 42 25 21 13 pc.3 i/o digital gpio pin mosi00 o spi0 1st mosi (master out, slave in) pin i2sdo o i2 s data output sc1rst o smartcard1 rst pin 43 26 22 14 pc.2 i/o digital gpio pin miso00 i spi0 1st miso (master in, slave out) pin i2sdi i i2 s data input sc1pwr o smartcard1 pwr pin 44 27 23 15 pc.1 i/o digital gpio pin spiclk0 i/o spi0 serial clock pin i2sbclk i/o i2s bit clock pin sc1dat i/o smartcard1 data pin 45 28 2 4 16 pc.0 i/o digital gpio pin spiss00 i/o spi0 1st slave select pin i2slrclk i/o i 2 s left right channel clock sc1clk o smartcard1 clock pin
n ano100(a) mar 31 , 201 5 page 44 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 46 pe.6 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. 47 29 pe.5 i/o digital gpio pin pwm 1ch1 i/o pwm 1 channel1 output 48 30 pb.11 i/o digital gpio pin tm r 3 o timer3 external counter input pwm 1ch0 i/o pwm 1 channel0 output miso00 i/o spi0 1st miso (master in, slave out) pin 49 31 pb.10 i/o digital gpio pin spiss01 i/o spi0 2nd slave select pin tm r 2 o timer2 external counter input mosi00 i/o spi0 1st mosi (master out, slave in) pin 50 32 pb.9 i/o digital gpio pin spiss11 i/o spi1 2nd slave select pin tm r 1 o timer1 external counter input nint0 i external interrupt 0 input pin 51 pe.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi00 i/o spi0 1st mosi (master out, slave in) pin 52 pe.3 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso00 i/o spi0 1st miso (master in, slave out) pin 53 pe.2 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. spiclk 0 o spi0 serial clock pin 54 pe.1 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. pwm 1ch3 i/o pwm 1 channel3 output spiss00 o spi0 1st slave select pin 55 pe.0 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package.
n ano100(a) mar 31 , 201 5 page 45 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 pwm 1ch2 i/o pwm 1 channel2 output i2smclk o i2s master clock output pin 56 pc.13 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. mosi11 o spi1 2nd mosi (master out, slave in) pin pwm1ch! o pwm1 channel1 output snooper i snooper pin nint0 i external interrupt 0 input pin i2c0sck o i2c0 clock pin 57 pc.12 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. miso11 i spi1 2nd miso (master in, slave out) pin pwm1ch0 o pwm1 channel 0 output nint0 i external interrupt 0 input pin i2c 0 sda i/o i2c 0 data i/o pin 58 33 pc.11 i/o digital gpio pin user program must enable pull - up resistor in lqfp 48 package. mosi10 o spi1 1st mosi (master out, slave in) pin tx1 o uart1 data transmitter output pin 59 34 pc.10 i/o digital gpio pin user program must enable pull - up resistor in lqfp 48 package. miso10 i spi1 1st miso (master in, slave out) pin rx1 i uart1 data receiver input pin 60 35 pc.9 i/o digital gpio pin user program must enable pull - up resistor in lqfp 48 package. spiclk 1 i/o spi1 serial clock pin i2c1sck i/o i2 c1 clock pin 61 36 pc.8 i/o digital gpio pin user program must enable pull - up resistor in lqfp 48 package. spiss10 i/o spi1 1st slave select pin mclk o ebi external clock output pin
n ano100(a) mar 31 , 201 5 page 46 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 i2c1sda i/o i2 c1 data i/o pin 62 37 25 17 pa.15 i/o digital gpio pin pwm 0ch3 i/o pwm 0 channel3 output i2smclk o i2s master clock output pin tc3 i timer3 capture input tx 0 o uart0 data transmitter output pin 63 38 26 18 pa.14 i/o digital gpio pin pwm 0ch2 i/o pwm 0 channel2 output ad15 i/o ebi address/data bus bit 15 tc2 i timer 2 capture input rx 0 i uart0 data receiver input pin 64 39 27 pa.13 i/o digital gpio pin pwm 0ch1 i/o pwm 0 channel1 output ad14 i/o ebi address/data bus bit 14 tc1 i timer1 capture input i2c 0 sc k i/o i2c 0 clock pin 65 40 28 pa.12 i/o digital gpio pin pwm0 ch0 i/o pwm0 channel0 output ad13 i/o ebi address/data bus bit 13 tc0 i timer 0 capture input i2c0sda i/o i2c 0 data i/o pin 66 41 29 19 ice_dat i/o serial wired debugger data pin pf.0 i/o digital gpio pin nint0 i external interrupt 0 input pin 67 42 30 20 ice_ck i serial wired debugger clock pin pf.1 i/o digital gpio pin clko o frequency divider output pin nint1 i external interrupt 1 input pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 33 vss p ground 70 43 31 avss ap ground pin for analog circuit 71 44 32 21 pa.0 i/o digital gpio pin
n ano100(a) mar 31 , 201 5 page 47 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 adc0 ai adc analog input 0 72 45 33 pa.1 i/o digital gpio pin adc1 ai adc analog input 1 ad12 i/o ebi address/data bus bit 12 73 46 34 22 pa.2 i/o digital gpio pin adc2 ai adc analog input 2 ad11 i/o ebi address/data bus bit 11 rx1 i uart1 data receiver input pin 74 47 35 23 pa.3 i/o digital gpio pin adc3 ai adc analog input 3 ad10 i/o ebi address/data bus bit 10 tx1 o uart1 data transmitter output pin 75 48 36 24 pa.4 i/o digital gpio pin adc4 ai adc analog input 4 ad9 i/o ebi address/data bus bit 9 i2c 0 sda i/o i2c 0 data i/o pin 76 49 37 25 pa.5 i/o digital gpio pin adc5 ai adc analog input 5 ad8 i/o ebi address/data bus bit 8 i2c0sc k i/o i2c0 clock pin 77 50 38 pa.6 i/o digital gpio pin adc6 ai adc analog input 6 ad7 i/o ebi address/data bus bit 7 tc3 i timer3 capture input pwm0ch3 o pwm0 channel3 output 78 51 39 pa.7 i/o digital gpio pin adc7 ai adc analog input 7 ad6 i/o ebi address/data bus bit 6 tc2 i timer2 capture input pwm0ch2 o pwm0 channel2 output 79 vref ap voltage reference input for adc 80 52 40 26 avdd ap power supply for internal analog circuit
n ano100(a) mar 31 , 201 5 page 48 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 81 pd.0 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. rx1 i uart1 data receiver input pin spiss2 0 i/o spi2 2nd slave select pin sc1clk o smartcard1 clock pin 82 pd.1 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. tx1 o uart1 data transmitter output pin spiclk 2 i/o spi2 serial clock pin sc1dat i/o smartcard1 data pin. 83 pd.2 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. rtsn1 o uart1 request to send output pin i2slrclk i/o i2s left right channel clock miso20 i spi2 1st miso (master in, slave out) pin sc1pwr o smartcard1 power pin 84 pd.3 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. ctsn1 i uart1 clear to send input pin i2sbclk i/o i2s bit clock pin mosi20 o spi2 1st mosi (master out, slave in) pin sc1rst o smartcard1 rst pin 85 pd.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2sdi i i2s data input miso21 i spi2 2nd miso (master in, slave out) pin sc1cd i smartcard1 card detect 86 pd.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2sdo o i2s data output mosi21 o spi2 2nd mosi (master out, slave in) pin
n ano100(a) mar 31 , 201 5 page 49 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 87 53 41 pc.7 i/o digital gpio pin ad5 i/o ebi address/data bus bit 5 tc1 i timer1 capture input pwm0ch1 o pwm1 channel1 output 88 54 42 27 pc.6 i/o digital gpio pin ad4 i/o ebi address/data bus bit 4 tc0 i timer 0 capture input sc1cd smartcard1 card detect pin pwm0ch0 o pwm0 channel0 output 89 55 pc.15 i/o digital gpio pin user program must enable pull - up resistor in lqfp48 package. ad3 i/o ebi address/data bus bit 3 tc0 i timer0 capture input pwm1ch2 o pwm1 channel1 output 90 56 pc.14 i/o digital gpio pin user program must enable pull - up resistor in lqfp 48 package. ad2 i /o ebi address/data bus bit 2 pwm1ch3 i/o pwm1 channel3 output 91 57 43 28 pb.15 i/o digital gpio pin n int1 i external interrupt 1 input pin snooper i snooper pin 92 58 44 29 xt1_out o external 4~24 mhz crystal output pin 93 59 45 30 xt1_in i external 4~24 mhz crystal input pin 94 60 46 31 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 pf.4 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2c 0 sda i/o i2c 0 data i/o pin
n ano100(a) mar 31 , 201 5 page 50 of 95 revision v 1 . 00 NANO100 (a) series datasheet pin no. pin name pin type description lqfp 100 lqfp 64 lqfp 48 qfn 33 98 p f.5 i/o digital gpio pin user program must enable pull - up resistor in lqfp64 and lqfp48 package. i2c 0 sc k i/o i 2 c 0 clock pin 99 63 47 32 pvss p pll ground 100 64 48 pb.8 i/o digital gpio pin adctrg i adc external trigger input. tm r 0 i timer0 external counter input nint0 i external interrupt 0 input pin note: pin type i=digital input, o=digital output; ai=analog input; ao= analog output; p=power pin; ap=analog power
n ano100(a) mar 31 , 201 5 page 51 of 95 revision v 1 . 00 NANO100 (a) series datasheet 4 block diagram 4.1 NANO100 b lock d iagram figure 4 - 1 numicro tm NANO100 b lock d iagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 6 4 / 3 2 k b c o r t e x - m 0 3 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c 1 . 5 / 2 . 5 v r e f 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 g p i o a , b , c , d , e , f p l l h x t l x t h i r c l i r c 1 0 - b a d c
n ano100(a) mar 31 , 201 5 page 52 of 95 revision v 1 . 00 NANO100 (a) series datasheet 4.2 nano120 b lock d iagram figure 4 - 2 numicro tm nano120 b lock d iagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 6 4 / 3 2 k b c o r t e x - m 0 3 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c t o u c h k e y u s b - 5 1 2 b u s b p h y 1 . 5 / 2 . 5 v r e f 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 g p i o a , b , c , d , e , f p l l h x t l x t h i r c l i r c 1 2 - b a d c 1 2 - b d a c
n ano100(a) mar 31 , 201 5 page 53 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5 functional descripti on 5.1 arm ? cortex? - m0 core 5.1.1 o verview the cortex? - m0 processor is a configurable, multistage, 32 - bit risc processor. it has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compati ble with other cortex - m profile processor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can b e entered as a result of an exception return. the following figure shows the functional controller of processor. figure 5 - 1 m0 functional block 5.1.2 f eatures ? a low gate count processor: ? armv6 - m thumb ? instruction set ? thumb - 2 technology ? armv6 - m compliant 24 - bit systick timer ? a 32 - bit hardware multiplier ? s upports little - endian data accesses ? capable of deterministic, fixed - latency, interrupt handling ? load/store - multiples and multi - cycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling ? c application binary interface compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the us e of pure c functions as interrupt handlers ? l ow p ower s leep mode entry using wait for interrupt (wfi), wait for e vent c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
n ano100(a) mar 31 , 201 5 page 54 of 95 revision v 1 . 00 NANO100 (a) series datasheet (wfe) instructions, or return from interrupt sleep - on - exit feature ? nvic: ? 32 external interrupt inputs, each with four levels of priority ? dedicated non - maskable interrupt (nmi) input ? supports for both level - sensitive and pulse - sensitive interrupt lines ? wake - up interrupt controller (wic), providing u ltra - low power sleep mode support ? debug support : ? four hardware breakpoi nts ? two watch points ? pr ogram counter sampling register (pcsr) f or non - intrusive code profiling ? single ste p and vector catch capabilities ? bus interfaces: ? single 32 - bit amba - 3 ahb - lite system interface provid ing simple integration to all system perip herals and memory ? single 32 - bit slave port that supports the dap (debug access port )
n ano100(a) mar 31 , 201 5 page 55 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.2 memory organization 5.2.1 overview nano 100 provides 4g - byte address ing space. the memory locations assigned to each on - chip modules are shown in following. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip module. nano 100 series only supports little - endian data format. 5.2.2 memory map the memory locations assigned to each on - chip controllers are shown in the following table . address space token modules flash & sram memory space 0x0000_0000 C 0x000 0 _ffff flash_ba flash memory space ( 64 kb) 0x2000_0000 C 0x2000_ 3 fff sram_ba sram memory space ( 16 kb) 0x6000_0000 --- 0x6001_ffff extmem_ba external memory space(128kb) ahb modules space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system management control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff dma_ba dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 C 0x5001_03ff ebi_ba external bus interface control registers apb1 modules space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wd t _ba watch - dog t imer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr0 1 _ba timer 0 and timer 1 control registers 0x4002_0000 C 0x4002_3fff i 2 c0_ba i2c 0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi 0 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwm 0 _ba pwm 0 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart 0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb fs device controller registers 0x400a_0000 C 0x400a_3fff reserved reserved 0x400d_0000 C 0x400d_3fff spi2_ba spi 2 with master/slave function control registers 0x400e_0000 C 0x400e_ 3 fff adc 1 0 _ba 1 2 - bit analog - digital - converter (adc 1 0 ) control registers apb2 modules space (0x4010_0000 ~ 0x401f_ffff) 0x4011_0000 C 0x4011_3fff tmr 23 _ba timer 2 and timer 3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i2c 1 interface control registers
n ano100(a) mar 31 , 201 5 page 56 of 95 revision v 1 . 00 NANO100 (a) series datasheet 0x4013_0000 C 0x4013_3fff spi 1 _ba spi 1 with master/slave function control registers 0x4014_0000 C 0x4014_3fff pwm 1 _ba pwm 1 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x4019_0000 C 0x4019_3fff sc0_ba smart card 0 control registers 0x401a_0000 C 0x401a_3fff i2s_ba i2s control registers 0x401b_0000 C 0x401b_3fff sc1_ba smart card 1 control registers system control space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers
n ano100(a) mar 31 , 201 5 page 57 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.3 nested vectored interrupt controller (nvic) 5.3.1 overview cortex - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic). it is closely coupled to the processor kernel and provides following features: 5.3.2 feature s ? nested and vectored interrupt support ? automatic processor state saving and restoration ? dynamic priority changing ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority o f the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r1 2 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handle s back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concu rrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the rea l - time capability. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n ano100(a) mar 31 , 201 5 page 58 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.4 system m anage r 5.4.1 overview s ystem manager mainly controls the power modes, wake - up source, syst em resets and system memory map. it also provides information about product id, chip reset, ip reset, and multi - function pin control. 5.4.2 features ? p ower modes and wake - up sources ? system resets ? system memory ma p ? system m anage r registers fo r : ? p roduct i d ? c hip and ip rese t ? m ulti - function al pin contro l
n ano100(a) mar 31 , 201 5 page 59 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.5 clock controller 5.5.1 overview the clock controller generates clock s for the whole chip , includ ing system clocks (cpu clock, hclkx, and pclkx) and all peripheral engine clocks . hclkx means ahb bus clock for peripherals on ahb bus. pclkx means apb bus clock for peripherals on apb bus. the clock controller also implements the power control function with the individually clock on/off control, c lock s ource select ion and a 4 - bit clock divider . the chip will not enter power - down mode until cpu set s the p ower d own enable bit (pd_en (pwrctl[6]) ) and cpu execut es the wfi instruction. in the power - down mode , clock controller turns off the external high frequency crystal , i nternal high freque ncy oscillator , and system clocks (cpu clock, hclkx, and pclkx) to reduce the power consumption to minimum. 5.5.2 f eatures ? generate s clocks for system clocks and all peripheral engine clocks ? each peripheral engine clock can be turned on/off . ? h igh frequency crystal, internal high frequency oscillator, and system clocks will be turned off when chip is in power - down mode .
n ano100(a) mar 31 , 201 5 page 60 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.6 flash memory controller (fmc) 5.6.1 overview t his chip is equipped with 32 k b /64k b on - chip embedded flash eprom for application progra m memory (aprom) that can be updated through isp procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on cortex - m0 cpu fetches code from aprom or ldrom decided by boot select ( cbs) in config0. by the way, this chip also provide s data flash region , the data flash is shared with original program memory and its start address is configurable and defined by user in config1. the data flash size is defined by user application request. 5.6.2 features ? ahb interface compatible ? run up to 32 mhz with zero wait state for discontinuous address read access ? 32 kb /64k b application program memory (aprom) ? 4 k b in system programming (isp) loader program memory (ldrom) ? programmable data flash start address and memory size with 512 bytes page erase unit ? in system program (isp)/in application program (iap) to update on chip flash eprom
n ano100(a) mar 31 , 201 5 page 61 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.7 external bus interface 5.7.1 overview this chip is equip ped with an external bus interface (ebi) to access external device. to save the connections between external devi c e and this chip, ebi support address bus and data bus multiplex mode. a lso , address latch enable (ale) signal is used to differentiate the address and data cycle . 5.7.2 features ? external devices with max. 64 kbytes size (8 - bit data width)/128 kbytes (16 - bit data width) supported ? supports v ariable external bus base clock (mclk) ? supports 8 - bit or 16 - bit data width ? supports v ariable data access time (tacc), address latch enable time (tale) and address hold time (tahd) ? addre ss bus and data bus multiplex mode supported to save the address pins ? configurable idle cycle supported for different access condition: write command finish (w2x), read - to - read (r2r), read - to - write (r2w) ? supports pdma and vdma transfer 5.8 general purpose i/o controller 5.8.1 overview the n u m icro tm NANO100 series have up to 51 general purpose i/o pins to be shared with other function pins depending on the chip configuration . these 51 pins are arranged in 6 ports named with gpioa, gpiob, gpioc, gpiod, gpioe and gpiof. each one of the 51 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be independ ently software configured as input, output, and open - drain mode. each i/o pin has a very weak individual pull - up resistor which is about 110 k ? ~300 k ? for vdd from 1.8 v to 3.6 v. 5.8.2 features ? three i/o modes: ? schmitt trigger input - only with high impendence ? pu sh - p ull output ? open - d rain output ? i/o pin configured as interrupt source with edge/level setting ? enabling the pin interrupt function will also enable the pin wake - up function
n ano100(a) mar 31 , 201 5 page 62 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.9 dma controller 5.9.1 overview the dma controller contains a four - channel peripheral direct memory access (pdma) controller and a one - channel video direct memory access (vdma) controller that transfers data to and from memory or transfer data to and from peripheral s.for vdma channel (dma ch0) , it only supports block transfer fro m memory to memory. for p dma channel (dma ch1~ch4), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. and for vdma channel (dma ch0) , there is a two - word buffer. user can stop the p dma or vdma operation by disable pdmacen ( pdma_csrx [0 ] ) or vdmacen (vdma_csr[0]), respectively . user can polling td_is ( pdma_isrx [1] or v dma_isrx [1]) or enable t d_ie ( pdma_ierx [1] or v dma_ierx [1]) and wait interrupt to check dma transfer complete . the dma controller can incr ease source or destination address, fixed or wrap around them as well. 5.9.2 features ? five channels: 1 vdma channel and 4 p dma channels. each channel can support a unidirectional transfer. ? vdma ? supports memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? p dma ? supports peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment transfer length in memo ry - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - word/byte transfer data width from/to peripheral ? supports address direction: increment, fixed, and wrap around ? amba ahb master/slave interface compatible, for data transfer and register read/write. ? hardware round robin priority scheme.
n ano100(a) mar 31 , 201 5 page 63 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.10 timer controller 5.10.1 overview this chip is equipped with four timer modules including timer0, timer1, timer2 and timer3 (timer0/1 is at apb1 and timer2/3 is at apb2), which allow user to easily implement a counting scheme or timing control for applications. the timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing , and so on. the timer can generate an interrupt signal upon timeout, or provide the current value of count during operation. 5.10.2 features ? independent clock source for each timer (tmrx_clk, x= 0, 1,2,3) ? time out period = (period of timer clock input) * (8 - bit p re - scale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / 25 mhz) * (2^8) * (2^24), if tclk = 25 mhz ? internal 8 - bit pre - sc ale counter ? internal 24 - bit up counter is readable th rough tdr (timer data register) ? supports o ne - shot, p eriodic and o utput t oggle o peration mode ? supports e xternal pin capture for interval measurement ? supports e xternal pin capture for timer counter reset ? supports i nter - timer trigger ? supports i nternal trigger event to adc and pdma 5.11 pulse width modulation (pwm) 5.11.1 overview this chip has two pwm controllers, each controller has 4 independent pwm outputs, ch 0~ ch3 , or as 2 complementary pwm pairs, ( ch0 , ch1 ), ( ch2 , ch 3) with 2 programmable dead - zone generators. each of the two pwm outputs, (ch0, ch1), (ch2, ch3), share the same 8 - bit prescaler, clock divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16) . each pwm output has independent 16 - bit pwm down - count counter for pwm period control, and 16 - bit comparators for pwm duty control . each dead - zone generator has two outpu ts. the first dead - zone generator output is ch0 and ch1, and for the second dead - zone generator , the output is ch2 and ch3 . the 2 sets of pwm controller total provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches 0 . pwm interrupt will be asserted when both pwm interrupt source and its corresponding enab le bit are active . each pwm output can be configured as one - shot mode to produce only one pwm cycle signal or continuous mode to output pwm waveform continuously. when dzen01 ( pwm x _ctl [4]) (x=0,1) is set, ch 0 and ch 1 perform complementary pwm paired function ; the paired pwm timing, period, duty and dead - time are determined by pwm channel 0 timer and dead - zone generator 0. similarly, when dzen 23 ( pwm x _ctl [5]) is set t he complementary pwm pair of ( ch2 , ch3 ) is controlled by pwm channel 2 . to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load ed into the 16 - bit down counter/ comparat or at the time down counter reaching 0 . the double buffering feature avoids glitch at
n ano100(a) mar 31 , 201 5 page 64 of 95 revision v 1 . 00 NANO100 (a) series datasheet pwm outputs. when the 16 - bit period down counter reaches 0 , the interrupt request is generated. if pwm output is set as continuous mode, when the down counter reaches 0 , it is reloaded with cn of pwm x_dutyy (y=0~3) register automatically then start decreas es , repeatedly. if the pwm output is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches 0 . the value of pwm counter com parator is used for pulse width modulation. the counter control logic changes the output level when down - counter value matches the value of compare register. the alternate feature of the pwm is digital input c apture function. if c apture function is enabled the pwm output pin is switched as capture input pin . the c apture channel 0 and pwm ch0 share one timer; and the c apture channel 1 and pwm ch1 share one timer, and etc. therefore user must setup the pwm timer before enabl ing c apture feature. after capture feature of channel 0 is enabled, the capture always latch es pwm ch0 timer value to capture rising latch register crl (pwm x _crl 0[15:0] ) when input channel has a rising transition and latche s pwm ch0 timer value to capture falling latch register cfl (pwm x _cf l 0[15:0] ) when input channel has a falling transition. capture channel 0 interrupt is programmable by setting crl_ie0 (pwmx_capinten[0]) for rising transition or cfl_ie0 ( pwm x _cap inten [1]) for falling transition . whenever capture rising event latched for c hannel 0, the pwm ch0 timer will be reload at this moment if the corresponding reload enable bit capreloadren0 (pwmx_capctl[6]) is set . the maximum captured frequency that pwm can capture is dominated by the capture interrupt latency. when capture interrup t occurs , software will do at least three steps, they are: read pwm x_ intsts to get interrupt source and r ead pwmx_crly/pwmx_cfly(y=0~3) to get capture value and finally write 1 to clear pwmx_intsts. i f interrupt latency will take time t0 to finish, the cap ture signal mustn t transient during this interval . i n this case, the maximum capture frequency will be 1/t0. 5.11.2 features pwm function : 5.11.2.1 ? two pwm controllers, each controller has 4 independent pwm outputs, ch 0~ ch3 , or as 2 complementary pwm pairs, ( ch0 , ch1 ), ( ch2 , ch 3) with 2 programmable dead - zone generators. ? up to 8 pwm channels or 4 pwm paired channels. ? up to 16 bits pwm counter width . ? pwm interrupt request synchronous with pwm period. ? one - shot or continuous mode. ? four dead - zone generators capture f unction : 5.11.2.2 ? timing control logic shared with pwm timer . ? 8 capture input channels shared with 8 pwm output channels. ? each channel supports one rising latch register crl (pwm x _crl 0[15:0] ), one falling latch register cfl (pwm x _cfl 0[15:0] ) and capture interrupt flag capi f 0 (pwmx_capintsts[0]) . ? e ight 16 - bit counter s for eight capture channels or four 32 - bit counter for four capture channels when cascade is enabled:when ch01casken (pwmx_capctl[13]) is set ,the original 16 - bit counter of channel 1 will combine with channel 0 s 16 - bit counter for channel 0 input capture counting and so does ch23casken
n ano100(a) mar 31 , 201 5 page 65 of 95 revision v 1 . 00 NANO100 (a) series datasheet (pwmx_capctl[29]) for channel 2,3 ? supports pdma transf er function for pwmx channel 0, 2
n ano100(a) mar 31 , 201 5 page 66 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.12 watchdog timer controller 5.12.1 overview the purpose of watchdog timer is to perform a system reset after the software running into a problem. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up cpu from power - down mode. the watchdog timer includes an 18 - bit free running co unter with programmable time - out intervals. 5.12.2 features ? 1 8 - bit free running wdt counter for watchdog timer time - out interval. ? s elect able time - out interval (2^4 ~ 2^18) and the t ime - out interval is 104 ms ~ 26.316 s ( if wdt_ clk = 10 k hz ) . ? reset period = ( 1 / 10 khz ) * 63 , if wdt_ clk = 10 khz .
n ano100(a) mar 31 , 201 5 page 67 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.13 rtc 5.13.1 overview real time clock (rtc) unit provides user the real time and calendar message. the clock source of rtc is from an external 32.768 khz crystal connected at pins x32i and x32o (reference to pin description ) or from an external 32.768 khz oscillator output fed at pin x32i. the rtc unit provides the time message (second, minute, hour) in time loading register (tlr) as well as calendar message (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. this unit offers alarm function that user can preset the alarm time in time alarm register (tar) and alarm calendar in calendar alarm register (car). the rtc unit supports periodic time tick and alarm match interrupts. the perio dic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is equal to alarm setting time registers tar and car, the alarm interrupt flag ( ai s (rtc_riir[0]) ) i s set and the alarm interrupt is requested if the alarm interrupt is enabled (aier (rtc_rier[0])=1) . the rtc time tick (if wake - up cpu function is enabled, ( twke (rtc_ttr[3]) ) high)) and alarm match can cause cpu wake - up from idle or power - down mode . 5.13.2 feature s ? there is a time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time. ? alarm register (second, minute, hour, day, month, year). ? 12 - hour or 24 - hour mode is selectable. ? leap year compensation automatically. ? day o f week counter. ? frequency compensate register (fcr). ? all time and calendar message is expressed in bcd code. ? supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second. ? supports rtc time tick and alarm m atch interrupt ? supports wake - up cpu from power - down mode. ? supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers.
n ano100(a) mar 31 , 201 5 page 68 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.14 uart controller 5.14.1 overview the uart c ontroller provides up to two channels of universal asynchronous r eceiver/transmitter (uart) modules and perform s normal speed uart, and support s flow control function. the universal asynchronous receiver/transmitter (uart) performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - s erial conversion on data transmitted from the cpu. the uart controller also supports irda (sir), lin master/slave and rs - 485 function mode s . 5.14.2 features ? full duplex, asynchronous communications. ? separate receiving / transmitting 16 byte s entry fifo for data payloads. ? supports hardware a uto - flow control function (ctsn, rtsn) and programmable (ctsn, rtsn) flow control trigger level. ? supports programmable baud rate generator for each channel. ? supports auto - baud rate detect function . ? supports programmab le receiver buffer trigger level. ? supports incoming data or ctsn to wake - up function. ? supports 9 bit receiver buffer time - out detection function . ? all uart channel s can be served by the p dma controller. ? programmable transmitting data delay time between the last stop bit leaving the tx - fifo and the de - assertion by setting dly( uart_ t mctl [ 23:16 ] ) register. ? supports irda sir f unction mode ? supports lin function mode. ? supports rs - 485 function mode.
n ano100(a) mar 31 , 201 5 page 69 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.15 smart card host interface (sc) 5.15.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/ removal . 5.15.2 features ? iso - 7816 - 3 t = 0, t = 1 compliant. ? emv2000 compliant ? u p to two iso - 7816 - 3 ports ? separate s receive/transmit 4 byte entry fifo for data payloads. ? programmable transmission clock frequency. ? programmable receiver buffer trigger level. ? programmable guard time selection (11 etu ~ 26 7 etu). ? a 24 - bit and two 8 bit timers for answer to request (atr) and waiting times processing. ? support s auto inverse convention function. ? support s transmitter and receiver error retry and error number limitation function. ? support s hardware activation sequence process. ? support s hardware warm reset sequence process. ? support s hardware deactivation sequence process. ? support s hardware auto deactivation sequence when detected the card removal. ? support s uart mode ? half duplex, asynchronous communications. ? separate s receiving / transmitting 4 bytes en try fifo for data payloads. ? support s programmable baud rate generator for each channel. ? support s programmable receiver buffer trigger level. ? programmable transmitting data delay time between the last stop bit leaving the tx - fifo and the de - assertion by set ting sc_egtr register. ? programmable even, odd or no parity bit generation and detection. ? programmable stop bit, 1 or 2 stop bit generation . 5.16 i 2 c 5.16.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exch ange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. serial, 8 - bit oriented bi - directional data transfers can be made up to 1 mbps. data is transferred between a master and a slave synchronously to scl on the sda line on a
n ano100(a) mar 31 , 201 5 page 70 of 95 revision v 1 . 00 NANO100 (a) series datasheet byte - by - byte basis. each data byte is 8 - bit long. there is one scl clock pulse for each data bit with the msb being transmitted f irst. an acknowledge bit follows each transferred byte. a transition on the sda line while scl is high is interpreted as a command (start or stop). each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the l ow period of scl and must be held stable during the high period of scl. the controllers on - chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c controller handles byte transfers autonomously. pull up re sistor is needed for i 2 c operation as these are open drain pins. the i 2 c controller is equipped with two slave address registers. the contents of the registers are irrelevant when i 2 c is in master mode. in the slave mode, the seven most significant bits must be loaded with the users own slave address. the i 2 c hardware will react if the contents of i2caddr are matched with the received slave address. this controller supports the general call (gc) function. if the gc all (i2csaddr[0]) bit is set this cont roller will respond to general call address (00h). clear gc bit to disable general call function. when gc all bit is set and the i 2 c is in slave mode, it can receive the general call address which is equal to 00h after master sends general call address to t he i 2 c bus, then it will follow status of gc mode. if it is in master mode, the ack bit must be cleared when it sends general call address of 00h to the i 2 c bus. the i 2 c - bus controller supports multiple address recognition with two address mask register. w hen the bit in the address mask register is set to one, it means the received corresponding address bit is dont - care. if the bit is set to 0 , that means the received corresponding register bit should be exact the same as address register .
n ano100(a) mar 31 , 201 5 page 71 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.16.2 features ? support s two i 2 c channels and both of them can a cts as master or slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? one built - in 14 - bit time - out counter req uest ing the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable clock divider allow s versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( two slave address es with mask option)
n ano100(a) mar 31 , 201 5 page 72 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.17 spi 5.17.1 ove rview the serial peripheral interface (spi) is a synchronous serial data communication protocol. devices communicate in master/slave mode with 4 - wire bi - direction interface. it is used to perform a serial - to - parallel conversion on data received from a peri pheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. the spi controller can be configured as a master or a slave device . the spi controller supports wake - up function. when this chip stays in power - down mode, it can be waked up chip by off - chip device. this controller supports variable serial clock for special application and 2 data channel transfer mode to connect 2 off - chip slave devices. the spi controller also supports p dma function to access the data buffer. 5.17.2 features ? up to two sets of spi controllers ? supports master (max. 16 mhz) or slave (max. 6 mhz) mode operation ? supports 1 bit data channel and 2 bit data channel transfer mode ? configurable bit length of a transaction from 8 to 32 bit s and configurable transaction number up to 2 of a transfer in burst mode, so the maximum bit length is 64 bits for each data transfer in burst mode ? supports msb first or lsb first transfer sequence ? two slave select lines supported in master mode ? configurable byte or word su spend mode ? supports byte re - ordering function ? supports variable serial clock in master mode ? provide dual fifo buffer s ? supports wake - up function ? supports pdma transfer ? supports 3 - wires, no slave select signal, bi - direction interface
n ano100(a) mar 31 , 201 5 page 73 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.18 i 2 s 5.18.1 overview the audio controller consists of i 2 s protocol to interface with external audio codec. two 8 word deep fifo for receiving path and transmitting path respectively and is capable of handling 8 - , 16 - , 24 - , 32 - bit word sizes. p dma controller handles the data movement between fifo and memory. 5.18.2 features ? support m aster mode and s lave mode ? capable of handling 8 - , 16 - , 24 - or 32 - bit word sizes ? supports m on aural and stereo audio data ? supports i 2 s and msb justified data format ? provides t wo 8 - level fifo data buffers, one for transmit ting and the other for receiv ing ? generates interrupt requests when buffer levels cross a programmable boundary ? support pdma transfer
n ano100(a) mar 31 , 201 5 page 74 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.19 usb 5.19.1 overview the usb controller is a usb 2.0 full - speed device controller. it is compliant with usb 2.0 full speed device specification and support s control/bulk/interrupt/isochronous transfer types. in this device controller, there are two main interfaces: the a p b bus and usb bus which comes from the usb phy transceiver. for the a p b b us, the cpu can program control registers through it. there is an internal 512 - byte sram as data buffer in this controller . for in token or out token transfer, it is necessary to write data to sram or read data from sram through the a p b interface. users need to allocate the effective starting address of sram for each endpoint buffer through buffer segmentation register (bufseg). this device controller contains 6 configurable endpoints. each endpoint can be configured as in or out endp oint. the function address of the device and endpoint number in each endpoint shall be configured properly in advance for receiving or transmitting a data packet correctly . the transmit ting/receiving length in each endpoint is defined in maximum payload re gister (mxpld) and the handshakes between host and device are also handled by it . there are four different interrupt events in this controller. they are the wake - up function, device plug - in or plug - out event, usb events, like in ack, out ack etc, and bus e vents, like suspend and resume, etc. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register ( usb_intsts ) to acknowledge what kind of events occurring, and then check the related usb endpoi nt status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint. a software - disable function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables the d rvse0 bit (usb_drvse0), the usb controller will force usb_dp and usb_dm to level low and usb device function is disabled (disconnected) . after disable the drvse0 bit, host will enumerate the usb device again. reference: universal serial bus specification r evision 2.0 5.19.2 features this universal serial bus (usb) performs a serial interface with a single connector type for attaching all usb peripherals to the host system. following is the feature list ing of this usb. ? compliant with usb 2.0 full - speed specificatio n. ? provide 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) . ? supports control/bulk/interrupt/isochronous transfer type. ? supports suspend function when no bus activity existing for 3 ms. ? provide 6 endpoints for configurable control/bulk/interrupt/isochronous transfer types ? 512 - byte sram buffer inside ? provide remote wake - up capability.
n ano100(a) mar 31 , 201 5 page 75 of 95 revision v 1 . 00 NANO100 (a) series datasheet 5.20 analog to digital converter (adc) 5.20.1 overview the nano1 00 s eries contain s one 1 2 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 external input channels and 1 internal channel . the a/d converter supports three operation modes: single, single - cycle scan and continuo us scan mode , and can be started by software , external stadc/pb.8 pin , timer event start. note th at the i/o pins used as adc analog input pins must configure the pin function ( pa_l_mfp ) to adc input and off digital function (gpioa_offd) should be turned on before adc function is enabled. 5.20.2 features ? analog input voltage range: 0~vref (max to 3.6v). ? 1 2 - bi t resolution and 8 - bits accuracy is guaranteed. ? up to 8 external analog input channels (channel0 ~ channel7), and 1 internal channel (channel10) converting four voltage sources ( internal band - gap voltage, internal temperature sensor output, avdd, and avss ) . ? maximum adc clock frequency is 16 mhz and each conversion is 21 clocks . ? three operating modes ? single mode: a/d conversion is performed one time on a specified channel. ? single - cycle scan mode: a/d conversion is performed one cycle on all specified channe ls with the sequence from the lowest numbered channel to the highest numbered channel. ? continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion. ? an a/d conversion can be started by ? software write 1 to adst bit ? external pin stadc ? selects one from four timer events (tmr0 , tmr 1 , tmr 2 and tmr 3 ) that enable adc and transfer ad results by pdma ? conversion results are held in data registers for each channel ? supports data registers to hold conversion resu lts for each channel. ? supports a/d conversion end interrupt to indicate the end of a/d conversion. ? supports two digital comparators to compare conversion result with a specified value. ? supports digital comparator interrupt to indicate that conversion resu lt meets setting condition.
n ano100(a) mar 31 , 201 5 page 76 of 95 revision v 1 . 00 NANO100 (a) series datasheet 6 application ci r cuit a v s s a v d d a v c c v s s v d d 4 ~ 2 4 m h z c r y s t a l 1 u f / / 1 0 n f 2 0 p 2 0 p d v c c 1 0 u f / 2 5 v 1 0 k p o w e r c r y s t a l r e s e t c i r c u i t n r e s e t x t 1 _ o u t l d o _ c a p n a n o 1 0 0 a n v d d v s s / r e s e t i c e _ d a t i c e _ c l k s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o s d a s c l 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i s s m o s i s p i c l k m i s o m o s i l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t x t 1 _ i n d v c c 4 . 7 k d v c c d v c c u a r t [ 1 ] r x t x v r e f i n c a s e v r e f = a v d d 1 u f / / 1 0 n f v r e f a v s s v c c
n ano100(a) mar 31 , 201 5 page 77 of 95 revision v 1 . 00 NANO100 (a) series datasheet 7 electrical character istic 7.1 absolute max i mum ratings symbol parameter min max unit dc power supply v dd ss - 0.3 + 3.6 v input voltage on five - volt tolerance pin v in v ss - 0.3 5.5 v input voltage on any other pin without five - volt tolerance pin v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 +85 ? c storage temperature t st - 55 +150 ? c maximum current into vdd - 150 ma maximum current out of vss - 150 ma maximum current sunk by a i/o pin - 25 ma maximum current sourced by a i/o pin - 25 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: gpio support s input 5v tolerance exce pt adc shared pins, pc.6 and pc.7 .
n ano100(a) mar 31 , 201 5 page 78 of 95 revision v 1 . 00 NANO100 (a) series datasheet 7.2 dc electrical characteristics (v dd - v ss =3.3v, t a = 25 ? c, f osc = 32 mhz unless otherwise specified.) parameter sym. specification test conditions min. typ. max. unit operation voltage v dd 1.8 - 3.6 v v dd = 1.8 v up to 32 mhz power ground v ss av ss - 0.3 - v ldo output voltage v ldo 1 1.62 1.8 1.98 v mcu operating in run or idle mode v ldo 2 1.66 v mcu operating in power - down mode analog operating voltage av dd v dd v operating current run mode @ xtal 12 mhz , hclk = 32 mhz i dd1 14 ma v dd = 3.6 v@ 32 mhz, enable all ip and pll i dd2 7.5 ma v dd = 3 . 6 v@ 32 mhz disable all ip and enable pll i dd3 12 ma v dd = 1.8 v@ 32 mhz enable all ip and pll i dd4 7 ma v dd = 1.8 v@ 32 mhz disable all ip and enable pll operating current run mode @ xtal 12mhz , hclk = 12mhz i dd5 5 ma v dd = 3.6 v@12mhz, enable all ip and disable pll i dd6 2.5 ma v dd = 3.6 v@12mhz, disable all ip and disable pll i dd7 4 ma v dd = 1.8 v@12mhz, enable all ip and disable pll i dd8 2 ma v dd = 1.8 v@12mhz, disable all ip and disable pll operating current run mode @ irc 12mhz , hclk = 12mhz i dd 9 6 ma v dd = 3.6 v@12mhz, enable all ip and disable pll i dd 10 2.3 ma v dd = 3.6 v@12mhz, disable all ip and disable pll i dd 11 5.7 ma v dd = 1.8 v@12mhz, enable all ip and disable pll i dd 12 2.2 ma v dd = 1.8 v@12mhz, disable all ip and disable pll
n ano100(a) mar 31 , 201 5 page 79 of 95 revision v 1 . 00 NANO100 (a) series datasheet parameter sym. specification test conditions min. typ. max. unit operating current run mode @ xtal 4mhz , hclk = 4mhz i dd 13 2.2 ma v dd = 3.6 v@4mhz, enable all ip and disable pll i dd1 4 1.1 ma v dd = 3.6 v@4mhz, disable all ip and disable pll i dd1 5 2 ma v dd = 1.8 v@4mhz, enable all ip and disable pll i dd1 6 1 ma v dd = 1.8 v@4mhz, disable all ip and disable pll operating current run mode @ xtal 32.768 khz , hclk = 32.768 khz i dd 17 90 ua v dd = 3.6 v@ 32.768 khz enable all ip and disable pll, i dd1 8 80 ua v dd = 3.6 v@ 32.768 khz disable all ip and disable pll i dd1 9 75 ua v dd = 1.8 v@ 32.768 khz enable all ip and disable pll i dd 20 72 ua v dd = 1.8 v@ 32.768 khz disable all ip and disable pll operating current run mode @ irc 10 khz , hclk = 10 khz i dd 21 80 ua v dd = 3.6 v@ 10 khz enable all ip and disable pll i dd 22 75 ua v dd = 3.6 v@ 10 khz disable all ip and disable pll i dd 23 67 ua v dd = 1.8 v@ 10 khz enable all ip and disable pll i dd 24 65 ua v dd = 1.8 v@ 10 khz disable all ip and disable pll operating current idle mode @ xtal 12 mhz , hclk = 32mhz i idle1 10.5 ma v dd = 3.6 v@ 32 mhz enable all ip and pll, i idle2 4.2 ma v dd = 3.6 v@ 32 mhz disable all ip and enable pll i idle3 9 ma v dd = 1.8 v@ 32 mhz enable all ip and pll i idle4 4 ma v dd = 1.8 v@ 32 mhz disable all ip and enable pll operating current idle mode @ xtal 12mhz , hclk = 12mhz i idle5 3.3 ma v dd = 3.6 v@12mhz, enable all ip and disable pll i idle6 0.7 m a v dd = 3.6 v@12mhz, disable all ip and disable pll i idle7 3 ma v dd = 1.8 v@12mhz, enable all ip and disable pll
n ano100(a) mar 31 , 201 5 page 80 of 95 revision v 1 . 00 NANO100 (a) series datasheet parameter sym. specification test conditions min. typ. max. unit i idle8 0.7 m a v dd = 1.8 v@12mhz, disable all ip and disable pll operating current idle mode @ irc 12mhz , hclk = 12mhz i idle 9 4.5 ma v dd = 3.6 v@12mhz, enable all ip and disable pll i idle 10 0.7 m a v dd = 3.6 v@12mhz, disable all ip and disable pll i idle 11 4.2 ma v dd = 1.8 v@12mhz, enable all ip and disable pll i idle 12 0.7 m a v dd = 1.8 v@12mhz, disable all ip and disable pll operating current idle mode @ xtal 4mhz , hclk = 4mhz i idle 13 1.7 ma v dd = 3.6 v@4mhz, enable all ip and disable pll i idle1 4 0.6 ma v dd = 3.6 v@4mhz, disable all ip and disable pll i idle1 5 1 ma v dd = 1.8 v@4mhz, enable all ip and disable pll i idle1 6 0.5 ma v dd = 1.8 v@4mhz, disable all ip and disable pll operating current idle mode @ xtal 32.768 khz , hclk = 32.768 khz i idle 17 85 ua v dd = 3.6 v@ 32.768 khz enable all ip and disable pll i idle1 8 75 ua v dd = 3.6 v@ 32.768 khz disable all ip and disable pll i idle1 9 70 ua v dd = 1.8 v@ 32.768 khz enable all ip and disable pll i idle 20 65 ua v dd = 1.8 v@ 32.768 khz disable all ip and disable pll operating current idle mode @ irc 10 khz , hclk = 10 khz i idle 21 80 ua v dd = 3.6 v@ 10 khz enable all ip and disable pll i idle 22 75 ua v dd = 3.6 v@ 10 khz disable all ip and disable pll i idle 23 65 ua v dd = 1.8 v@ 10 khz enable all ip and disable pll i idle 24 63 ua v dd = 1.8 v@ 10 khz disable all ip and disable pll standby current power - down mode i pwd1 1.5 ? a v dd = 3.6 v, rtc off, all clock stop w ith ram retenstion, io no loading
n ano100(a) mar 31 , 201 5 page 81 of 95 revision v 1 . 00 NANO100 (a) series datasheet parameter sym. specification test conditions min. typ. max. unit i pwd 2 1.0 ? a v dd = 1.8 v, rtc off, all clock stop w ith ram retenstion, io no loading i pwd 3 3 ? a v dd = 3.6 v, rtc o n , all clock stop except 32.768 khz w ith ram retenstion, io no loading i pwd 4 2.5 ? a v dd = 1.8 v, rtc o n , all clock stop except 32.768 khz w ith ram retenstion, io no loading input pu ll up resistor pa, pb, pc, pd, pe , pf r in 40 k v dd = 3. 3v 98 k v dd = 1.8v input leakage current pa, pb, pc, pd, pe , pf i lk - 0.1 - + 0.1 ? a v dd = 3 . 3 v, 0 n ano100(a) mar 31 , 201 5 page 82 of 95 revision v 1 . 00 NANO100 (a) series datasheet 3. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between vdd and the closest vss pin of the device. 4. for ensuring power stability, a 1 uf or higher capacitor must be connected between ldo pin and the closest vss pin of the device. also a 100nf bypass capacitor between ldo and vss help suppressing output noise 7.3 ac electrical characteristics 7.3.1 external input clock parameter sym. specification s test conditions min. typ. max. unit clock high time t chcx 1 0 - ns clock low time t clcx 1 0 - ns clock rise time t clch 2 - 1 5 ns clock fall time t chcl 2 - 1 5 ns 7.3.2 external 4~24 mhz xtal oscillator parameter sym. specification s test conditions min. typ. max. unit oscillator frequency f hxtal 4 12 24 mhz vdd = 1.8v ~ 3.6v temperature t hxtal - 40 - +85 o c operating current i hxtal 0.3 ma vdd = 3.0v typical crystal application circuits 7.3.2.1 crystal c1 c2 r 4mhz ~ 24 mhz optional ( depend on crystal s pecification ) without t c l c l t c l c x t c h c x t c l c h t c h c l x t 1 _ i n x t 1 _ o u t c 1 r 1 c 2
n ano100(a) mar 31 , 201 5 page 83 of 95 revision v 1 . 00 NANO100 (a) series datasheet figure 7 - 1 typical crystal application circuit 7.3.3 external 32.768 khz crystal parameter sym. specification s test conditions min. typ. max. unit oscillator frequency fl xtal 32.768 khz vdd = 1.8v ~ 3.6v temperature tl xtal - 40 - +85 o c operating current i hxtal 1.2 ? a vdd = 3 .0v 7.3.4 internal 12 mhz oscillator parameter sym. specification s test conditions min. typ. max. unit supply voltage [1] v hrc 1.8 v calibrated internal oscillator frequency f hrc 11.88 12 12.12 mhz 25 o c, v dd = 3v 10.8 12 13.2 mhz - 40 o c~+85 o c, v dd = 1.8v~3.6v 11. 88 12 12. 12 mhz - 40 o c~+85 o c, v dd = 1.8v~3.6v enable 32.768k crystal oscillator and set trim_sel[1:0]=10 operating current i hrc tbd ma note: internal oscillator operation voltage comes from ldo. 7.3.5 internal 10 khz oscillator parameter sym. specification test conditions min. typ. max. unit supply voltage [1] v lrc 1.8 v center frequency f lrc 7 10 13 khz 25 o c, v dd = 3v 5 10 15 khz - 40 o c~+85 o c, v dd = 1.8v~3.6v operating current i lrc 0.7 ? a v dd = 3v note: internal oscillator operation voltage comes from ldo. 7.4 analog characteristics 7.4.1 1 2 - bit adc parameter sym. specification s test conditions min. typ. max. unit
n ano100(a) mar 31 , 201 5 page 84 of 95 revision v 1 . 00 NANO100 (a) series datasheet parameter sym. specification s test conditions min. typ. max. unit operating voltage av dd 2.0 3.6 v av dd = v dd operating current i adc tbd ma av dd = v dd = 3.0 v resolution r adc 1 2 b it reference voltage v ref 1.5 a vdd v reference input current (avg.) i ref 320 ? a adc input voltage v in 0 v ref v conversion time t conv 1.25 ? s sampling rate f sps 800k hz v dd = 3 v integral non - linearity error inl 4 8 lsb differential non - linearity dnl - 1~+ 4 - 1~+ 8 lsb gain error e g 16 lsb offset error e offset 4 lsb absolute error e abs - 16 lsb adc clock frequency f adc 0.25 1 6 m hz clock cycle ad cyc 21 cycle internal capacitance c in - 3.2 - pf internal resist ance r in - 200 - monotonic - guaranteed - 7.4.2 brown - out detector parameter sym. specification s test conditions min. typ. max. unit operating voltage v bod 1.8 3.6 v quiescent current i bod 1 ? a av dd = 3.0v, bod enable d bod17 detection level v b17dt1 1.6 1.7 1.8 v 25 o c v b17dt2 1.5 1.7 1.9 v - 40~85 o c bod20 detection level v b20dt1 1.9 2.0 2.1 v 25 o c v b20dt2 1.8 2.0 2.2 v - 40~85 o c bod25 detection level v b25dt1 2.4 2.5 2.6 v 25 o c v b25dt2 2.2 2.5 2.8 v - 40~85 o c
n ano100(a) mar 31 , 201 5 page 85 of 95 revision v 1 . 00 NANO100 (a) series datasheet 7.4.3 power - on reset parameter sym. specification s test conditions min. typ. max. unit reset voltage v por - 1.6 - v quiescent current i por - 1 - n a ldo output > r eset voltage 7.4.4 temperature sensor parameter sym. specification s test conditions min. typ. max. unit detection temperature t det - 40 +125 o c operating current i temp - 5 - ? a gain v tg - - 1.6 4 - mv/ o c offset v to - 750 - mv temp eature at 0 o c note: internal operation voltage comes form ldo. 7.4.5 internal voltage reference parameter sym. specification s test conditions min. typ. max. unit operating voltage a v dd 1.8 - 3.6 v 1.5v voltage reference v ref1 - 1.5 - v av dd >= 1.8v 2.5v voltage reference v ref2 - 2.5 - v av dd >= 2.8v stable time t reftab - 1 - ms operating current i vref - 30 - ? a av dd = 3v 7.4.6 usb phy specification s usb phy dc electrical characteristics 7.4.6.1 symbol parameter conditions min. typ. max. unit v ih input high (driven) 2.0 - v v il input low - 0.8 v v di differential input sensitivity |padp - padm| 0.2 - v v cm differential common - mode range includes v di range 0.8 - 2.5 v v se single - ended receiver threshold 0.8 - 2.0 v receiver hysteresis 200 mv
n ano100(a) mar 31 , 201 5 page 86 of 95 revision v 1 . 00 NANO100 (a) series datasheet v ol output low (driven) 0 - 0.3 v v oh output high (driven) 2.8 - 3.6 v v crs output signal cross voltage 1.3 - 2.0 v r pu pull - up resistor 1.425 - 1.575 k r pd pull - down resistor 14.25 - 15.75 k v trm termination voltage for upstream port pull up (rpu) 3.0 - 3.6 v z drv driver output resistance steady state drive* 10 c in transceiver capacitance pin to gnd - 20 pf *driver output resistance doesnt include series resistor resistance. usb phy full - speed driver elevtrical characteristics 7.4.6.2 symbol parameter conditions min. typ. max. unit t fr rise time c l =50p 4 - 20 ns t ff fall time c l =50p 4 - 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 - 111.11 % usb phy power dissipation 7.4.6.3 symbol parameter conditions min. typ. max. unit i vddreg (full speed) vddd and vddreg supply current (steady state) standby 50 ua usb ldo dc electrical characteristics 7.4.6.4 symbol parameter conditions min. typ. max. unit vbus 5 v v33 o utput voltage 3.3 v iop o peration current 100 ua
n ano100(a) mar 31 , 201 5 page 87 of 95 revision v 1 . 00 NANO100 (a) series datasheet 8 package dimension s 8.1 lqfp 100 (14x14x1.4 mm footprint 2.0 mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6
n ano100(a) mar 31 , 201 5 page 88 of 95 revision v 1 . 00 NANO100 (a) series datasheet 8.2 lqfp 64 (7x7x1.4 mm footprint 2.0 mm)
n ano100(a) mar 31 , 201 5 page 89 of 95 revision v 1 . 00 NANO100 (a) series datasheet
n ano100(a) mar 31 , 201 5 page 90 of 95 revision v 1 . 00 NANO100 (a) series datasheet 8.3 lqfp 48 (7x7x1.4 mm footprint 2.0 mm)
n ano100(a) mar 31 , 201 5 page 91 of 95 revision v 1 . 00 NANO100 (a) series datasheet 8.4 qfn 33 (5x5x0.8 mm footprint 0.5 mm)
n ano100(a) mar 31 , 201 5 page 92 of 95 revision v 1 . 00 NANO100 (a) series datasheet
n ano100(a) mar 31 , 201 5 page 93 of 95 revision v 1 . 00 NANO100 (a) series datasheet 9 revision history date revision description 2011.05.31 0.001 initial release 2011.08.22 0.002 modified the e lectrical c haracteristic s section 2011.10.31 0.003 1. change d the max spi speed to 16 mhz 2. adc pin without 5v tolerance 3. modif ied the e lectrical c haracteristics section 4. remove d xt1_in and xt1_out g pio (pf.2/pf.3) shared function 5. modif ied pin diagram and pin description 6. remove d timer continuous operation mode and uart wakeup function 7. revise d the product selection table 8. fix ed typos . 2011.12.31 0.004 1. update d pin diagram and pin d escription 2. update d the dc e lectrical c h aracteristics section 201 2 . 04 . 09 0.00 5 1. remove d uart1 shared function from pin - 26 to pi n - 29 in NANO100 lqfp100 package 2. add ed detailed description of i2cintsts register (i2cx_ba + 0x04) 2013.06 . 27 0.006 1. remove d nano110/nano130 series information. 2. updated NANO100 series selection code in section 3.1. 3. updated NANO100 product selection guide in section 3.2. 4. removed gpiof[ 2 ] and gpiof[ 3 ] of multiple function port f in section 5. 4 .5. 5. added a n ote f or gpiof_puen, bits [15:6] and [3:2] are reserved in section 5. 8 .6 . 2013.07. 30 0.007 1. updated NANO100 product selection guide in section 3.2. 2. added NANO100 qfn33 pin diagram and description in section 3.3.1.4 and 3.4.1. 2014.12.29 0.008 1. updated NANO100 product selection guide in section 3. 2 . 2. changed timer0/1 ch0/1 to timer x (x=0, 1, 2, 3) in the timer
n ano100(a) mar 31 , 201 5 page 94 of 95 revision v 1 . 00 NANO100 (a) series datasheet controller section. 2015.03.31 1.00 1. updated e lectrical characteristics tbd items in chapter 7 . 2. added a pplicat ion c ircuit in chapter 6 . 3. added a noto that gpio support s input 5v tolerance except adc shared pins, pc.6 and pc.7 in section 7 .1. 4. updated the value of capacitor connected with ldo pin to be 1uf in section 7 .2. 5. updated e xternal 4~24 mhz xtal application circuit in section 7 .3.4. 6. updated 12 - bit adc c haracteristi cs in section 7 .4.1. 7. added brown - out detector c haracteristics in a full operatin g temperature range in section 7 .4.2.
n ano100(a) mar 31 , 201 5 page 95 of 95 revision v 1 . 00 NANO100 (a) series datasheet i mportant notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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